#include "skeleton64.dtsi" #include #include #include #include #include #include #include #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} / { model = "Qualcomm Technologies, Inc. MSM8917"; compatible = "qcom,msm8917"; qcom,msm-id = <303 0x0>, <308 0x0>, <309 0x0>; interrupt-parent = <&wakegic>; chosen { bootargs = "sched_enable_hmp=1"; }; aliases { sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 for SD card */ spi3 = &spi_3; spi6 = &spi_6; i2c2 = &i2c_2; i2c5 = &i2c_5; i2c3 = &i2c_3; i2c4 = &i2c_4; }; firmware: firmware { android { compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; parts = "vbmeta,boot,system,vendor,dtbo,recovery"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,avb"; status = "ok"; }; }; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; other_ext_mem: other_ext_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x85b00000 0x0 0xd00000>; }; modem_mem: modem_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x86800000 0x0 0x5500000>; }; adsp_fw_mem: adsp_fw_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8bd00000 0x0 0x1100000>; }; wcnss_fw_mem: wcnss_fw_region@0 { compatible = "removed-dma-pool"; no-map; reg = <0x0 0x8ce00000 0x0 0x700000>; }; venus_mem: venus_region@0 { compatible = "shared-dma-pool"; reusable; alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; alignment = <0 0x400000>; size = <0 0x0800000>; }; qseecom_mem: qseecom_region@0 { compatible = "shared-dma-pool"; reusable; alignment = <0 0x400000>; size = <0 0x1000000>; }; qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; size = <0 0x400000>; }; adsp_mem: adsp_region@0 { compatible = "shared-dma-pool"; reusable; alignment = <0 0x400000>; size = <0 0x400000>; }; cont_splash_mem: splash_region@83000000 { reg = <0x0 0x90000000 0x0 0x1400000>; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; reusable; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; alignment = <0x0 0x400000>; size = <0 0xd5000>; }; }; clocks { xo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; clock-output-names = "xo_board"; }; }; soc: soc { }; vendor: vendor { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; }; }; #include "msm8917-pinctrl.dtsi" #include "msm8917-camera.dtsi" #include "msm8917-cpu.dtsi" #include "msm8917-pm.dtsi" #include "msm8917-ion.dtsi" #include "msm8917-coresight.dtsi" #include "msm8917-bus.dtsi" #include "msm8917-mdss.dtsi" #include "msm8917-mdss-pll.dtsi" #include "msm-arm-smmu-8917.dtsi" #include "msm8917-gpu.dtsi" #include "msm8917-vidc.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; interrupt-parent = <&intc>; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; }; dcc: dcc@b3000 { compatible = "qcom,dcc"; reg = <0xb3000 0x1000>, <0xb4000 0x2000>; reg-names = "dcc-base", "dcc-ram-base"; clocks = <&gcc GCC_DCC_CLK>; clock-names = "apb_pclk"; qcom,save-reg; }; wakegic: wake-gic { compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic"; interrupts-extended = <&wakegic GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; reg = <0x601d0 0x1000>, <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ reg-names = "vmpm", "ipc"; qcom,num-mpm-irqs = <64>; interrupt-controller; interrupt-parent = <&intc>; #interrupt-cells = <3>; }; wakegpio: wake-gpio { compatible = "qcom,mpm-gpio"; interrupt-controller; interrupt-parent = <&intc>; #interrupt-cells = <2>; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 2 0xff08>, <1 3 0xff08>, <1 4 0xff08>, <1 1 0xff08>; clock-frequency = <19200000>; }; qcom,sps { compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; }; thermal_zones: thermal-zones {}; mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; rpm_sw_dump { qcom,dump-size = <0x28000>; qcom,dump-id = <0xea>; }; pmic_dump { qcom,dump-size = <0x10000>; qcom,dump-id = <0xe4>; }; vsense_dump { qcom,dump-size = <0x1000>; qcom,dump-id = <0xe9>; }; tmc_etf_dump { qcom,dump-size = <0x10000>; qcom,dump-id = <0xf0>; }; tmc_etr_reg_dump { qcom,dump-size = <0x1000>; qcom,dump-id = <0x100>; }; tmc_etf_reg_dump { qcom,dump-size = <0x1000>; qcom,dump-id = <0x101>; }; misc_data_dump { qcom,dump-size = <0x1000>; qcom,dump-id = <0xe8>; }; c0_scandump { qcom,dump-size = <0x10100>; qcom,dump-id = <0x130>; }; c100_scandump { qcom,dump-size = <0x10100>; qcom,dump-id = <0x131>; }; c200_scandump { qcom,dump-size = <0x10100>; qcom,dump-id = <0x132>; }; c300_scandump { qcom,dump-size = <0x10100>; qcom,dump-id = <0x133>; }; c0_context { qcom,dump-size = <0x800>; qcom,dump-id = <0x0>; }; c1_context { qcom,dump-size = <0x800>; qcom,dump-id = <0x1>; }; c2_context { qcom,dump-size = <0x800>; qcom,dump-id = <0x2>; }; c3_context { qcom,dump-size = <0x800>; qcom,dump-id = <0x3>; }; l1_icache100 { qcom,dump-size = <0x8800>; qcom,dump-id = <0x60>; }; l1_icache101 { qcom,dump-size = <0x8800>; qcom,dump-id = <0x61>; }; l1_icache102 { qcom,dump-size = <0x8800>; qcom,dump-id = <0x62>; }; l1_icache103 { qcom,dump-size = <0x8800>; qcom,dump-id = <0x63>; }; l1_dcache100 { qcom,dump-size = <0x9000>; qcom,dump-id = <0x80>; }; l1_dcache101 { qcom,dump-size = <0x9000>; qcom,dump-id = <0x81>; }; l1_dcache102 { qcom,dump-size = <0x9000>; qcom,dump-id = <0x82>; }; l1_dcache103 { qcom,dump-size = <0x9000>; qcom,dump-id = <0x83>; }; }; tsens0: tsens@4a8000 { compatible = "qcom,msm8937-tsens"; reg = <0x4a8000 0x1000>, <0x4a9000 0x1000>, <0xa4000 0x1000>; reg-names = "tsens_srot_physical", "tsens_tm_physical", "tsens_eeprom_physical"; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tsens-upper-lower"; #thermal-sensor-cells = <1>; }; timer@b120000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0xb120000 0x1000>; clock-frequency = <19200000>; frame@b121000 { frame-number = <0>; interrupts = <0 8 0x4>, <0 7 0x4>; reg = <0xb121000 0x1000>, <0xb122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = <0 9 0x4>; reg = <0xb123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = <0 10 0x4>; reg = <0xb124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = <0 11 0x4>; reg = <0xb125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = <0 12 0x4>; reg = <0xb126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = <0 13 0x4>; reg = <0xb127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = <0 14 0x4>; reg = <0xb128000 0x1000>; status = "disabled"; }; }; qcom,rmtfs_sharedmem@00000000 { compatible = "qcom,sharedmem-uio"; reg = <0x00000000 0x00180000>; reg-names = "rmtfs"; qcom,client-id = <0x00000001>; }; restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>, <0x193d100 0x4>; reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; qcom,mpm2-sleep-counter@4a3000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0x4a3000 0x1000>; clock-frequency = <32768>; }; cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <1 7 IRQ_TYPE_LEVEL_HIGH>; }; slim_msm: slim@c140000 { cell-index = <1>; compatible = "qcom,slim-ngd"; reg = <0xc140000 0x2c000>, <0xc104000 0x2a000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>, <0 180 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; qcom,apps-ch-pipes = <0x600000>; qcom,ea-pc = <0x230>; status = "disabled"; }; blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; }; blsp1_uart1: uart@78af000 { /* BLSP1 UART1 */ compatible = "qcom,msm-hsuart-v14"; #address-cells = <0>; #interrupt-cells = <1>; reg = <0x78af000 0x200>, <0x7884000 0x1f000>; reg-names = "core_mem", "bam_mem"; interrupt-parent = <&blsp1_uart1>; interrupts = <0 1 2>; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; interrupt-map = <0 &intc 0 107 0 1 &intc 0 238 0 2 &tlmm 1 0>; interrupt-map-mask = <0xffffffff>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; qcom,bam-tx-ep-pipe-index = <0>; qcom,bam-rx-ep-pipe-index = <1>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart1_sleep>; pinctrl-1 = <&blsp1_uart1_active>; qcom,msm-bus,name = "blsp1_uart1"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0x7884000 0x1f000>; interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; qcom,summing-threshold = <10>; }; dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */ #dma-cells = <4>; compatible = "qcom,sps-dma"; reg = <0x7ac4000 0x1f000>; interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; qcom,summing-threshold = <10>; }; /* IO Expander SX150xq */ /* BLSP1 QUP4 */ i2c_4: i2c@78b8000 { compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b8000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_4_active>; pinctrl-1 = <&i2c_4_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 10 64 0x20000020 0x20>, <&dma_blsp1 11 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; rpm_bus: qcom,rpm-smd { compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ }; rpmcc: qcom,rpmcc { compatible = "qcom,rpmcc-qm215"; #clock-cells = <1>; }; gcc: qcom,gcc@1800000 { compatible = "qcom,gcc-msm8917", "syscon"; reg = <0x1800000 0x80000>, <0x00a6018 0x00004>; reg-names = "cc_base", "gpu-bin"; qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>; vdd_cx-supply = <&pm8937_s2_level>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "bi_tcxo"; #clock-cells = <1>; #reset-cells = <1>; }; cpu_debug: syscon@0b01101c { compatible = "syscon"; reg = <0x0b01101c 0x4>; }; debugcc: qcom,cc-debug { compatible = "qcom,qm215-debugcc"; reg = <0x1874000 0x4>, <0xb01101c 0x8>; reg-names = "cc_base", "meas"; qcom,gcc = <&gcc>; qcom,cpu = <&cpu_debug>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo_clk_src"; #clock-cells = <1>; }; gcc_mdss: qcom,gcc-mdss@1800000 { compatible = "qcom,gcc-mdss-qm215"; reg = <0x1800000 0x80000>; clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>; clock-names = "pclk0_src", "byte0_src"; #clock-cells = <1>; }; apsscc: qcom,clock-cpu@b011050 { compatible = "qcom,cpu-clock-qm215"; reg = <0xb011050 0x8>, <0xb016000 0x34>, <0x00a412c 0x8>, <0xb011200 0x100>; reg-names = "apcs-c1-rcg-base", "apcs_pll1", "efuse", "spm_c1_base"; cpu-vdd-supply = <&apc_vreg_corner>; vdd_dig_ao-supply = <&pm8916_s1_level_ao>; vdd_hf_pll-supply = <&pm8916_l7_ao>; clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0_AO_OUT_MAIN>; clock-names = "xo_ao", "gpll0_ao" ; qcom,speed0-bin-v0-c1 = < 0 0>, < 960000000 1>, < 1094400000 2>, < 1248000000 3>, < 1401000000 4>; qcom,speed1-bin-v0-c1 = < 0 0>, < 960000000 1>, < 1094400000 2>, < 1248000000 3>, < 1401000000 4>, < 1497600000 5>; qcom,speed2-bin-v0-c1 = < 0 0>, < 960000000 1>, < 1094400000 2>, < 1209600000 3>; qcom,speed3-bin-v0-c1 = < 0 0>, < 960000000 1>, < 1094400000 2>, < 1248000000 3>, < 1305600000 4>; #clock-cells = <1>; }; msm_cpufreq: qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "cpu0_clk"; clocks = <&apsscc APCS_MUX_C1_CLK>; qcom,governor-per-policy; qcom,cpufreq-table = < 960000 >, < 1094400 >, < 1209600 >, < 1248000 >, < 1305600 >, < 1401000 >, < 1497600 >; }; i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b6000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 6 64 0x20000020 0x20>, <&dma_blsp1 7 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x78b7000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr"; reg = <0x7af5000 0x600>; interrupt-names = "qup_irq"; interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&gcc GCC_BLSP2_AHB_CLK>, <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <84>; dmas = <&dma_blsp2 4 64 0x20000020 0x20>, <&dma_blsp2 5 32 0x20000020 0x20>; dma-names = "tx", "rx"; status = "disabled"; }; spi_3: spi@78b7000 { /* BLSP1 QUP3 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0x78b7000 0x600>, <0x7884000 0x1f000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi3_default &spi3_cs0_active>; pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; clock-names = "iface_clk", "core_clk"; qcom,infinite-mode = <0>; qcom,use-bam; qcom,use-pinctrl; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <8>; qcom,bam-producer-pipe-index = <9>; qcom,master-id = <86>; status = "disabled"; }; usb_otg: usb@78db000 { compatible = "qcom,hsusb-otg"; reg = <0x78db000 0x400>, <0x6c000 0x200>; reg-names = "core", "phy_csr"; #address-cells = <1>; #size-cells = <1>; ranges; interrupts = <0 134 IRQ_TYPE_LEVEL_HIGH>, <0 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "core_irq", "async_irq"; hsusb_vdd_dig-supply = <&pm8937_l2>; HSUSB_1p8-supply = <&pm8937_l7>; HSUSB_3p3-supply = <&pm8937_l13>; qcom,vdd-voltage-level = <0 1200000 1200000>; vbus_otg-supply = <&smbcharger_charger_otg>; qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */ qcom,hsusb-otg-mode = <3>; /* OTG mode */ qcom,hsusb-otg-otg-control = <2>; /* PMIC */ qcom,dp-manual-pullup; qcom,phy-dvdd-always-on; qcom,boost-sysclk-with-streaming; qcom,axi-prefetch-enable; qcom,enable-sdp-typec-current-limit; qcom,hsusb-otg-delay-lpm; qcom,msm-bus,name = "usb2"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <87 512 0 0>, <87 512 80000 0>, <87 512 6000 6000>; clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>, <&rpmcc BIMC_USB_A_CLK>, <&rpmcc SNOC_USB_A_CLK>, <&rpmcc PNOC_USB_A_CLK>, <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, <&rpmcc CXO_SMD_OTG_CLK>; clock-names = "iface_clk", "core_clk", "sleep_clk", "bimc_clk", "snoc_clk", "pcnoc_clk", "phy_csr_clk", "xo"; qcom,bus-clk-rate = <595200000 200000000 100000000>; qcom,max-nominal-sysclk-rate = <133330000>; resets = <&gcc GCC_USB_HS_BCR>, <&gcc GCC_QUSB2_PHY_BCR>, <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; reset-names = "core_reset", "phy_reset", "phy_por_reset"; qcom,usbbam@78c4000 { compatible = "qcom,usb-bam-msm"; reg = <0x78c4000 0x17000>; interrupt-parent = <&intc>; interrupts = <0 135 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-type = <1>; qcom,usb-bam-num-pipes = <4>; qcom,usb-bam-fifo-baseaddr = <0x08605000>; qcom,ignore-core-reset-ack; qcom,disable-clk-gating; qcom,usb-bam-max-mbps-highspeed = <400>; qcom,reset-bam-on-disconnect; qcom,pipe0 { label = "hsusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x6044000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <0>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0xe00>; qcom,descriptor-fifo-offset = <0xe00>; qcom,descriptor-fifo-size = <0x200>; }; }; }; ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 100, 8); /* 769 MB/s */ BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */ BW_OPP_ENTRY( 297, 8); /* 2270 MB/s */ BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */ BW_OPP_ENTRY( 556, 8); /* 4248 MB/s */ BW_OPP_ENTRY( 595, 8); /* 4541 MB/s */ BW_OPP_ENTRY( 672, 8); /* 5126 MB/s */ BW_OPP_ENTRY( 740, 8); /* 5645 MB/s */ }; cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@408000 { compatible = "qcom,bimc-bwmon2"; reg = <0x408000 0x300>, <0x401000 0x200>; reg-names = "base", "global_base"; interrupts = ; qcom,mport = <0>; qcom,target-dev = <&cpu_cpu_ddr_bw>; }; cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devbw"; governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; operating-points-v2 = <&ddr_bw_opp_table>; }; cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { compatible = "qcom,arm-memlat-cpugrp"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; cpu0_computemon: qcom,cpu0-computemon { compatible = "qcom,arm-compute-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; qcom,core-dev-table = < 998400 MHZ_TO_MBPS(230, 8) >, < 1094400 MHZ_TO_MBPS(557, 8) >, < 1497600 MHZ_TO_MBPS(557, 8) >; }; }; qcom,wdt@b017000 { compatible = "qcom,msm-watchdog"; reg = <0xb017000 0x1000>; reg-names = "wdt-base"; interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, <0 4 IRQ_TYPE_LEVEL_HIGH>; qcom,bark-time = <11000>; qcom,pet-time = <10000>; qcom,ipi-ping; qcom,wakeup-enable; }; qcom,memshare { compatible = "qcom,memshare"; qcom,client_1 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x200000>; qcom,client-id = <0>; qcom,allocate-boot-time; label = "modem"; }; qcom,client_2 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x300000>; qcom,client-id = <2>; label = "modem"; }; mem_client_3_size: qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x0>; qcom,client-id = <1>; label = "modem"; }; }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, <0x2400000 0x800000>, <0x2c00000 0x800000>, <0x3800000 0x200000>, <0x200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; }; qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */ }; qcom,msm-imem@8600000 { compatible = "qcom,msm-imem"; reg = <0x08600000 0x1000>; /* Address and size of IMEM */ ranges = <0x0 0x08600000 0x1000>; #address-cells = <1>; #size-cells = <1>; mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 0x8>; }; dload_type@1c { compatible = "qcom,msm-imem-dload-type"; reg = <0x1c 0x4>; }; restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 0x4>; }; boot_stats@6b0 { compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 0x20>; }; kaslr_offset@6d0 { compatible = "qcom,msm-imem-kaslr_offset"; reg = <0x6d0 0xc>; }; pil@94c { compatible = "qcom,msm-imem-pil"; reg = <0x94c 0xc8>; }; diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; }; }; jtag_mm0: jtagmm@61bc000 { compatible = "qcom,jtagv8-mm"; reg = <0x61bc000 0x1000>, <0x61b0000 0x1000>; reg-names = "etm-base", "debug-base"; qcom,coresight-jtagmm-cpu = <&CPU0>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; }; jtag_mm1: jtagmm@61bd000 { compatible = "qcom,jtagv8-mm"; reg = <0x61bd000 0x1000>, <0x61b2000 0x1000>; reg-names = "etm-base", "debug-base"; qcom,coresight-jtagmm-cpu = <&CPU1>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; }; jtag_mm2: jtagmm@61be000 { compatible = "qcom,jtagv8-mm"; reg = <0x61be000 0x1000>, <0x61b4000 0x1000>; reg-names = "etm-base", "debug-base"; qcom,coresight-jtagmm-cpu = <&CPU2>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; }; jtag_mm3: jtagmm@61bf000 { compatible = "qcom,jtagv8-mm"; reg = <0x61bf000 0x1000>, <0x61b6000 0x1000>; reg-names = "etm-base", "debug-base"; qcom,coresight-jtagmm-cpu = <&CPU3>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; }; qcom,ipc-spinlock@1905000 { compatible = "qcom,ipc-spinlock-sfpb"; reg = <0x1905000 0x8000>; qcom,num-locks = <8>; }; apcs: syscon@0b011008 { compatible = "syscon"; reg = <0x0b011008 0x04>; }; tcsr_mutex_block: syscon@01905000 { compatible = "syscon"; reg = <0x01905000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; rpm_msg_ram: memory@60000 { compatible = "qcom,rpm-msg-ram"; reg = <0x60000 0x8000>; }; smem_mem: smem_region@86300000 { no-map; reg = <0x86300000 0x100000>; }; smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; qcom,rpm-msg-ram = <&rpm_msg_ram>; hwlocks = <&tcsr_mutex 3>; }; smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = ; qcom,ipc = <&apcs 0 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = ; qcom,ipc = <&apcs 0 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; sleepstate_smp2p_out: sleepstate-out { qcom,entry-name = "sleepstate"; #qcom,smem-state-cells = <1>; }; sleepstate_smp2p_in: qcom,sleepstate-in { qcom,entry-name = "sleepstate_see"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p_sleepstate { compatible = "qcom,smp2p-sleepstate"; qcom,smem-states = <&sleepstate_smp2p_out 0>; interrupt-parent = <&sleepstate_smp2p_in>; interrupts = <0 0>; interrupt-names = "smp2p-sleepstate-in"; }; smp2p-wcnss { compatible = "qcom,smp2p"; qcom,smem = <451>, <431>; interrupts = ; qcom,ipc = <&apcs 0 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; wcnss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; wcnss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smd { compatible = "qcom,smd"; modem { interrupts = ; qcom,ipc = <&apcs 0 12>; qcom,smd-edge = <0>; qcom,remote-pid = <1>; label = "mpss"; qcom,smd-channels = "IPCRTR"; qcom,modem_qrtr { qcom,net-id = <1>; qcom,low-latency; }; qcom,diag { qcom,smd-channels = "DIAG"; }; qcom,diag_cntl { qcom,smd-channels = "DIAG_CNTL"; }; qcom,diag_cmd { qcom,smd-channels = "DIAG_CMD"; }; qcom,diag_dci { qcom,smd-channels = "DIAG_2"; }; qcom.diag_dci_cmd { qcom,smd-channels = "DIAG_2_CMD"; }; }; adsp { interrupts = ; qcom,ipc = <&apcs 0 8>; qcom,smd-edge = <1>; qcom,remote-pid = <2>; mbox-names = "adsp_smem"; label = "adsp"; qcom,smd-channels = "IPCRTR"; qcom,adsp_qrtr { qcom,net-id = <1>; qcom,low-latency; }; qcom,diag { qcom,smd-channels = "DIAG"; }; qcom,diag_cntl { qcom,smd-channels = "DIAG_CNTL"; }; qcom,apr_tal_rpmsg { qcom,smd-channels = "apr_audio_svc"; }; }; wcnss { interrupts = ; qcom,ipc = <&apcs 0 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; label = "wcnss"; qcom,smd-channels = "IPCRTR"; qcom,wcnss_qrtr { qcom,net-id = <1>; qcom,low-latency; }; qcom,diag { qcom,smd-channels = "APPS_RIVA_DATA"; }; qcom,diag_cntl { qcom,smd-channels = "APPS_RIVA_CTRL"; }; }; rpm { interrupts = ; qcom,ipc = <&apcs 0 0>; qcom,smd-edge = <15>; label = "rpm"; rpm_requests: rpm_requests@0 { compatible = "qcom,rpm-smd"; qcom,smd-channels = "rpm_requests"; }; }; }; qcom,smsm { compatible = "qcom,smsm"; #address-cells = <1>; #size-cells = <0>; qcom,ipc-1 = <&apcs 0 13>; qcom,ipc-2 = <&apcs 0 9>; qcom,ipc-3 = <&apcs 0 19>; apps_smsm: apps@0 { reg = <0>; #qcom,smem-state-cells = <1>; }; modem_smsm: modem@1 { reg = <1>; interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; }; adsp_smsm: adsp@2 { reg = <2>; interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; }; wcnss_smsm: wcnss@3 { reg = <3>; interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smdpkt { compatible = "qcom,smdpkt"; qcom,smdpkt-data5-cntl { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA5_CNTL"; qcom,smdpkt-dev-name = "smdcntl0"; }; qcom,smdpkt-data22 { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA22"; qcom,smdpkt-dev-name = "smd22"; }; qcom,smdpkt-data40-cntl { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA40_CNTL"; qcom,smdpkt-dev-name = "smdcntl8"; }; qcom,smdpkt-data2 { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA2"; qcom,smdpkt-dev-name = "at_mdm0"; }; qcom,smdpkt-apr-apps2 { qcom,smdpkt-edge = "adsp"; qcom,smdpkt-ch-name = "apr_apps2"; qcom,smdpkt-dev-name = "apr_apps2"; }; qcom,smdpkt-apps-riva-bt-acl { qcom,smdpkt-edge = "wcnss"; qcom,smdpkt-ch-name = "APPS_RIVA_BT_ACL"; qcom,smdpkt-dev-name = "smd2"; qcom,smdpkt-fragmented-read; }; qcom,smdpkt-apps-riva-bt-cmd { qcom,smdpkt-edge = "wcnss"; qcom,smdpkt-ch-name = "APPS_RIVA_BT_CMD"; qcom,smdpkt-dev-name = "smd3"; qcom,smdpkt-fragmented-read; }; qcom,smdpkt-mbalbridge { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "MBALBRIDGE"; qcom,smdpkt-dev-name = "smd4"; }; qcom,smdpkt-apps-riva-ant-cmd { qcom,smdpkt-edge = "wcnss"; qcom,smdpkt-ch-name = "APPS_RIVA_ANT_CMD"; qcom,smdpkt-dev-name = "smd5"; }; qcom,smdpkt-apps-riva-ant-data { qcom,smdpkt-edge = "wcnss"; qcom,smdpkt-ch-name = "APPS_RIVA_ANT_DATA"; qcom,smdpkt-dev-name = "smd6"; }; qcom,smdpkt-data1 { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA1"; qcom,smdpkt-dev-name = "smd7"; }; qcom,smdpkt-data4 { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA4"; qcom,smdpkt-dev-name = "smd8"; }; qcom,smdpkt-data11 { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA11"; qcom,smdpkt-dev-name = "smd11"; }; qcom,smdpkt-data21 { qcom,smdpkt-edge = "modem"; qcom,smdpkt-ch-name = "DATA21"; qcom,smdpkt-dev-name = "smd21"; }; }; qcom_tzlog: tz-log@8600720 { compatible = "qcom,tz-log"; reg = <0x08600720 0x2000>; }; bam_dmux: qcom,bam_dmux@4044000 { compatible = "qcom,bam_dmux"; reg = <0x4044000 0x19000>; qcom,rx-ring-size = <32>; qcom,max-rx-mtu = <4096>; qcom,fast-shutdown; qcom,no-cpu-affinity; qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; qcom,smem-state-names = "pwrctrl", "pwrctrlack"; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "dmux", "ctrl", "ack"; }; sdcc1_ice: sdcc1ice@7803000 { compatible = "qcom,ice"; reg = <0x7803000 0x8000>; interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq"; interrupts = <0 312 IRQ_TYPE_LEVEL_HIGH>, <0 313 IRQ_TYPE_LEVEL_HIGH>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&gcc SDCC1_ICE_CORE_CLK_SRC>, <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; qcom,op-freq-hz = <200000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm", "qcom,sdhci-msm-cqe"; reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>, <0x7803000 0x8000>; reg-names = "hc_mem", "core_mem", "cqhci_mem", "cqhci_ice"; interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; qcom,large-address-bus; qcom,devfreq,freq-table = <50000000 200000000>; qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <13 651>; qcom,pm-qos-cpu-groups = <0x0f>; qcom,pm-qos-cmdq-latency-us = <13 651>; qcom,pm-qos-legacy-latency-us = <13 651>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <9>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1046 3200>, /* 400 KB/s*/ <78 512 52286 160000>, /* 20 MB/s */ <78 512 65360 200000>, /* 25 MB/s */ <78 512 130718 400000>, /* 50 MB/s */ <78 512 130718 400000>, /* 100 MB/s */ <78 512 261438 800000>, /* 200 MB/s */ <78 512 261438 800000>, /* 400 MB/s */ <78 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <200000000 100000000>; /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>; qcom,scaling-lower-bus-speed-mode = "DDR52"; status = "disabled"; }; sdhc_2: sdhci@7864900 { compatible = "qcom,sdhci-msm"; reg = <0x7864900 0x500>, <0x7864000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,large-address-bus; qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <13 651>; qcom,pm-qos-cpu-groups = <0x0f>; qcom,pm-qos-legacy-latency-us = <13 651>; qcom,msm-bus,name = "sdhc2"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ <81 512 1046 3200>, /* 400 KB/s*/ <81 512 52286 160000>, /* 20 MB/s */ <81 512 65360 200000>, /* 25 MB/s */ <81 512 130718 400000>, /* 50 MB/s */ <81 512 261438 800000>, /* 100 MB/s */ <81 512 261438 800000>, /* 200 MB/s */ <81 512 1338562 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; qcom,devfreq,freq-table = <50000000 200000000>; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; qcom_seecom: qseecom@85b00000 { compatible = "qcom,qseecom"; reg = <0x85b00000 0x800000>; reg-names = "secapp-region"; qcom,hlos-num-ce-hw-instances = <1>; qcom,hlos-ce-hw-instance = <0>; qcom,qsee-ce-hw-instance = <0>; qcom,disk-encrypt-pipe-pair = <2>; qcom,support-fde; qcom,msm-bus,name = "qseecom-noc"; qcom,msm-bus,num-cases = <4>; qcom,msm-bus,num-paths = <1>; qcom,support-bus-scaling; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 0 0>, <55 512 120000 1200000>, <55 512 393600 3936000>; clocks = <&gcc CRYPTO_CLK_SRC>, <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; qcom,ce-opp-freq = <100000000>; }; qcom,iris-fm { compatible = "qcom,iris_fm"; }; qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x04080000 0x100>, <0x0194f000 0x010>, <0x01950000 0x008>, <0x01951000 0x008>, <0x04020000 0x040>, <0x01871000 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; interrupts = ; vdd_mss-supply = <&pm8937_s1>; vdd_cx-supply = <&pm8937_s2_level>; vdd_cx-voltage = ; vdd_mx-supply = <&pm8937_l3_level_ao>; vdd_mx-uV = ; vdd_pll-supply = <&pm8937_l7>; qcom,vdd_pll = <1800000>; vdd_mss-uV = ; clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>, <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>; clock-names = "xo", "iface_clk", "bus_clk", "mem_clk"; qcom,proxy-clock-names = "xo"; qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk"; qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sequential-fw-load; qcom,override-acc-1 = <0x80800000>; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,qdsp6v56-1-8-inrush-current; qcom,reset-clk; qcom,iommu-vmid = <0xF>; /* VMID_MSS_MSA */ /* Inputs from mss */ /* TBD */ interrupts-extended = <&modem_smp2p_in 0 0>, <&modem_smp2p_in 1 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 3 0>, <&modem_smp2p_in 7 0>; interrupt-names = "qcom,err-fatal", "qcom,err-ready", "qcom,proxy-unvote", "qcom,stop-ack", "qcom,shutdown-ack"; /* Output to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; memory-region = <&modem_mem>; }; qcom,lpass@c200000 { compatible = "qcom,pil-tz-generic"; reg = <0xc200000 0x00100>; interrupts = ; vdd_cx-supply = <&pm8937_s2_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>, <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc CRYPTO_CLK_SRC>; clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,scm_core_clk_src-freq = <80000000>; qcom,mas-crypto = <&mas_crypto>; qcom,pas-id = <1>; qcom,complete-ramdump; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <423>; qcom,sysmon-id = <1>; qcom,ssctl-instance-id = <0x14>; qcom,firmware-name = "adsp"; /* Inputs from lpass */ /* TBD */ interrupts-extended = <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, <&adsp_smp2p_in 3 0>; interrupt-names = "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", "qcom,stop-ack"; /* Output to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; memory-region = <&adsp_fw_mem>; }; qcom,pronto@a21b000 { compatible = "qcom,pil-tz-generic"; reg = <0x0a21b000 0x3000>; interrupts = ; vdd_pronto_pll-supply = <&pm8937_l7>; proxy-reg-names = "vdd_pronto_pll"; vdd_pronto_pll-uV-uA = <1800000 18000>; clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>, <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc CRYPTO_CLK_SRC>; clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,scm_core_clk_src = <80000000>; qcom,mas-crypto = <&mas_crypto>; qcom,pas-id = <6>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <422>; qcom,sysmon-id = <6>; qcom,ssctl-instance-id = <0x13>; qcom,firmware-name = "wcnss"; /* Inputs from wcnss */ /* TBD */ interrupts-extended = <&wcnss_smp2p_in 0 0>, <&wcnss_smp2p_in 1 0>, <&wcnss_smp2p_in 2 0>, <&wcnss_smp2p_in 3 0>; interrupt-names = "qcom,err-fatal", "qcom,err-ready", "qcom,proxy-unvote", "qcom,stop-ack"; /* Output to wcnss */ qcom,smem-states = <&wcnss_smp2p_out 0>; qcom,smem-state-names = "qcom,force-stop"; memory-region = <&wcnss_fw_mem>; }; qcom,venus@1de0000 { compatible = "qcom,pil-tz-generic"; reg = <0x1de0000 0x4000>; vdd-supply = <&gdsc_venus>; qcom,proxy-reg-names = "vdd"; clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, <&gcc GCC_VENUS0_AHB_CLK>, <&gcc GCC_VENUS0_AXI_CLK>, <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc CRYPTO_CLK_SRC>; clock-names = "core_clk", "iface_clk", "bus_clk", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,scm_core_clk_src-freq = <80000000>; qcom,msm-bus,name = "pil-venus"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <63 512 0 0>, <63 512 0 304000>; qcom,mas-crypto = <&mas_crypto>; qcom,pas-id = <9>; qcom,proxy-timeout-ms = <100>; qcom,firmware-name = "venus"; memory-region = <&venus_mem>; }; qcom_rng: qrng@e3000 { compatible = "qcom,msm-rng"; reg = <0xe3000 0x1000>; qcom,msm-rng-iface-clk; qcom,no-qrng-config; qcom,msm-bus,name = "msm-rng-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <1 618 0 0>, /* No vote */ <1 618 0 800>; /* 100 MB/s */ clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "iface_clk"; }; qcom_crypto: qcrypto@720000 { compatible = "qcom,qcrypto"; reg = <0x720000 0x20000>, <0x704000 0x20000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <2>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; qcom,msm-bus,name = "qcrypto-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 393600 393600>; clocks = <&gcc CRYPTO_CLK_SRC>, <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; qcom,use-sw-ahash-algo; qcom,use-sw-hmac-algo; qcom,use-sw-aead-algo; qcom,ce-opp-freq = <100000000>; }; qcom_cedev: qcedev@720000 { compatible = "qcom,qcedev"; reg = <0x720000 0x20000>, <0x704000 0x20000>; reg-names = "crypto-base","crypto-bam-base"; interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>; qcom,bam-pipe-pair = <1>; qcom,ce-hw-instance = <0>; qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,msm-bus,name = "qcedev-noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <55 512 0 0>, <55 512 393600 393600>; clocks = <&gcc CRYPTO_CLK_SRC>, <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; qcom,ce-opp-freq = <100000000>; }; qcom,adsprpc-mem { compatible = "qcom,msm-adsprpc-mem-region"; memory-region = <&adsp_mem>; }; qcom,msm_fastrpc { compatible = "qcom,msm-fastrpc-legacy-compute"; qcom,msm_fastrpc_compute_cb { compatible = "qcom,msm-fastrpc-legacy-compute-cb"; label = "adsprpc-smd"; iommus = <&apps_iommu 0x2008 0x7>; sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>; }; }; spi_6: spi@7af6000 { /* BLSP2 QUP2 */ compatible = "qcom,spi-qup-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "spi_physical", "spi_bam_physical"; reg = <0x7af6000 0x600>, <0x7ac4000 0x1d000>; interrupt-names = "spi_irq", "spi_bam_irq"; interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; pinctrl-names = "spi_default", "spi_sleep"; pinctrl-0 = <&spi6_default &spi6_cs0_active>; pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>; clocks = <&gcc GCC_BLSP2_AHB_CLK>, <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>; clock-names = "iface_clk", "core_clk"; qcom,infinite-mode = <0>; qcom,use-bam; qcom,use-pinctrl; qcom,ver-reg-exists; qcom,bam-consumer-pipe-index = <6>; qcom,bam-producer-pipe-index = <7>; qcom,master-id = <84>; status = "disabled"; }; qcom,wcnss-wlan@a000000 { compatible = "qcom,wcnss_wlan"; reg = <0xa000000 0x280000>, <0xb011008 0x4>, <0xa21b000 0x3000>, <0x3204000 0x100>, <0x3200800 0x200>, <0xa100400 0x200>, <0xa205050 0x200>, <0xa219000 0x20>, <0xa080488 0x8>, <0xa080fb0 0x8>, <0xa08040c 0x8>, <0xa0120a8 0x8>, <0xa012448 0x8>, <0xa080c00 0x1>; reg-names = "wcnss_mmio", "wcnss_fiq", "pronto_phy_base", "riva_phy_base", "riva_ccu_base", "pronto_a2xb_base", "pronto_ccpu_base", "pronto_saw2_base", "wlan_tx_phy_aborts","wlan_brdg_err_source", "wlan_tx_status", "alarms_txctl", "alarms_tactl", "pronto_mcu_base"; interrupts = <0 145 IRQ_TYPE_EDGE_RISING>, <0 146 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>; qcom,pronto-vddcx-supply = <&pm8937_s2_level>; qcom,pronto-vddpx-supply = <&pm8937_l5>; qcom,iris-vddxo-supply = <&pm8937_l7>; qcom,iris-vddrfa-supply = <&pm8937_l19>; qcom,iris-vddpa-supply = <&pm8937_l9>; qcom,iris-vdddig-supply = <&pm8937_l5>; qcom,iris-vddxo-voltage-level = <1800000 0 1800000>; qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>; qcom,iris-vddpa-voltage-level = <3300000 0 3300000>; qcom,iris-vdddig-voltage-level = <1800000 0 1800000>; qcom,vddmx-voltage-level = ; qcom,vddcx-voltage-level = ; qcom,vddpx-voltage-level = <1800000 0 1800000>; qcom,iris-vddxo-current = <10000>; qcom,iris-vddrfa-current = <100000>; qcom,iris-vddpa-current = <515000>; qcom,iris-vdddig-current = <10000>; qcom,pronto-vddmx-current = <0>; qcom,pronto-vddcx-current = <0>; qcom,pronto-vddpx-current = <0>; pinctrl-names = "wcnss_default", "wcnss_sleep", "wcnss_gpio_default"; pinctrl-0 = <&wcnss_default>; pinctrl-1 = <&wcnss_sleep>; pinctrl-2 = <&wcnss_gpio_default>; gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>, <&tlmm 79 0>, <&tlmm 80 0>; clocks = <&rpmcc CXO_SMD_WLAN_CLK>, <&rpmcc RPM_SMD_RF_CLK2>; clock-names = "xo", "rf_clk"; qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>, <&apps_smsm 12>; qcom,smem-state-names = "tx-enable", "tx-rings-empty", "wake-state"; qcom,has-autodetect-xo; qcom,is-pronto-v3; qcom,has-pronto-hw; qcom,has-vsys-adc-channel; qcom,wcnss-adc_tm = <&pm8937_adc_tm>; }; ssc_sensors: qcom,msm-ssc-sensors { compatible = "qcom,msm-ssc-sensors"; }; }; #include "pm8937-rpm-regulator.dtsi" #include "msm8917-regulator.dtsi" #include "pm8937.dtsi" #include "msm-gdsc-8916.dtsi" #include "msm8917-thermal.dtsi" &gdsc_venus { clock-names = "bus_clk", "core_clk"; clocks = <&gcc GCC_VENUS0_AXI_CLK>, <&gcc GCC_VENUS0_VCODEC0_CLK>; status = "okay"; }; &gdsc_venus_core0 { qcom,support-hw-trigger; clock-names ="core0_clk"; clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>; status = "okay"; }; &gdsc_mdss { clock-names = "core_clk", "bus_clk"; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AXI_CLK>; status = "okay"; }; &gdsc_jpeg { clock-names = "core_clk", "bus_clk"; clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, <&gcc GCC_CAMSS_JPEG_AXI_CLK>; status = "okay"; }; &gdsc_vfe { clock-names = "core_clk", "bus_clk", "micro_clk", "csi_clk"; clocks = <&gcc GCC_CAMSS_VFE0_CLK>, <&gcc GCC_CAMSS_VFE_AXI_CLK>, <&gcc GCC_CAMSS_MICRO_AHB_CLK>, <&gcc GCC_CAMSS_CSI_VFE0_CLK>; status = "okay"; }; &gdsc_vfe1 { clock-names = "core_clk", "bus_clk", "micro_clk", "csi_clk"; clocks = <&gcc GCC_CAMSS_VFE1_CLK>, <&gcc GCC_CAMSS_VFE1_AXI_CLK>, <&gcc GCC_CAMSS_MICRO_AHB_CLK>, <&gcc GCC_CAMSS_CSI_VFE1_CLK>; status = "okay"; }; &gdsc_cpp { clock-names = "core_clk", "bus_clk"; clocks = <&gcc GCC_CAMSS_CPP_CLK>, <&gcc GCC_CAMSS_CPP_AXI_CLK>; status = "okay"; }; &gdsc_oxili_gx { clock-names = "core_root_clk", "gfx_clk"; clocks =<&gcc GFX3D_CLK_SRC>, <&gcc GCC_OXILI_GFX3D_CLK>; qcom,enable-root-clk; qcom,clk-dis-wait-val = <0x5>; status = "okay"; }; /* GPU overrides */ &msm_gpu { qcom,gpu-speed-bin-vectors = <0x6018 0x80000000 31>, <0x0164 0x00000400 9>; /delete-node/qcom,gpu-pwrlevels; qcom,gpu-pwrlevel-bins { #address-cells = <1>; #size-cells = <0>; compatible="qcom,gpu-pwrlevel-bins"; qcom,gpu-pwrlevels-0 { #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <0>; qcom,initial-pwrlevel = <3>; /* TURBO */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <598000000>; qcom,bus-freq = <7>; qcom,bus-min = <7>; qcom,bus-max = <7>; }; /* NOM+ */ qcom,gpu-pwrlevel@1 { reg = <1>; qcom,gpu-freq = <523200000>; qcom,bus-freq = <6>; qcom,bus-min = <5>; qcom,bus-max = <7>; }; /* NOM */ qcom,gpu-pwrlevel@2 { reg = <2>; qcom,gpu-freq = <484800000>; qcom,bus-freq = <5>; qcom,bus-min = <4>; qcom,bus-max = <6>; }; /* SVS+ */ qcom,gpu-pwrlevel@3 { reg = <3>; qcom,gpu-freq = <400000000>; qcom,bus-freq = <4>; qcom,bus-min = <3>; qcom,bus-max = <5>; }; /* SVS */ qcom,gpu-pwrlevel@4 { reg = <4>; qcom,gpu-freq = <270000000>; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; }; /* XO */ qcom,gpu-pwrlevel@5 { reg = <5>; qcom,gpu-freq = <19200000>; qcom,bus-freq = <0>; qcom,bus-min = <0>; qcom,bus-max = <0>; }; }; qcom,gpu-pwrlevels-1 { #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <1>; qcom,initial-pwrlevel = <3>; /* TURBO */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <650000000>; qcom,bus-freq = <8>; qcom,bus-min = <8>; qcom,bus-max = <8>; }; /* NOM+ */ qcom,gpu-pwrlevel@1 { reg = <1>; qcom,gpu-freq = <523200000>; qcom,bus-freq = <6>; qcom,bus-min = <5>; qcom,bus-max = <7>; }; /* NOM */ qcom,gpu-pwrlevel@2 { reg = <2>; qcom,gpu-freq = <484800000>; qcom,bus-freq = <5>; qcom,bus-min = <4>; qcom,bus-max = <6>; }; /* SVS+ */ qcom,gpu-pwrlevel@3 { reg = <3>; qcom,gpu-freq = <400000000>; qcom,bus-freq = <4>; qcom,bus-min = <3>; qcom,bus-max = <5>; }; /* SVS */ qcom,gpu-pwrlevel@4 { reg = <4>; qcom,gpu-freq = <270000000>; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; }; /* XO */ qcom,gpu-pwrlevel@5 { reg = <5>; qcom,gpu-freq = <19200000>; qcom,bus-freq = <0>; qcom,bus-min = <0>; qcom,bus-max = <0>; }; }; qcom,gpu-pwrlevels-2 { #address-cells = <1>; #size-cells = <0>; qcom,speed-bin = <2>; qcom,initial-pwrlevel = <1>; /* NOM */ qcom,gpu-pwrlevel@0 { reg = <0>; qcom,gpu-freq = <465000000>; qcom,bus-freq = <7>; qcom,bus-min = <5>; qcom,bus-max = <7>; }; /* SVS+ */ qcom,gpu-pwrlevel@1 { reg = <1>; qcom,gpu-freq = <400000000>; qcom,bus-freq = <4>; qcom,bus-min = <3>; qcom,bus-max = <5>; }; /* SVS */ qcom,gpu-pwrlevel@2 { reg = <2>; qcom,gpu-freq = <270000000>; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <3>; }; /* XO */ qcom,gpu-pwrlevel@3 { reg = <3>; qcom,gpu-freq = <19200000>; qcom,bus-freq = <0>; qcom,bus-min = <0>; qcom,bus-max = <0>; }; }; }; };