// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include #include #include #include #include #include #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "common.h" #include "vdd-level-lagoon.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner); enum { P_BI_TCXO, P_CAM_CC_PLL0_OUT_EVEN, P_CAM_CC_PLL0_OUT_MAIN, P_CAM_CC_PLL1_OUT_EVEN, P_CAM_CC_PLL1_OUT_MAIN, P_CAM_CC_PLL2_OUT_EARLY, P_CAM_CC_PLL2_OUT_MAIN, P_CAM_CC_PLL3_OUT_MAIN, P_CORE_BI_PLL_TEST_SE, }; static const struct parent_map cam_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_0[] = { "bi_tcxo", "cam_cc_pll0_out_even", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL1_OUT_EVEN, 3 }, { P_CAM_CC_PLL2_OUT_MAIN, 4 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_1[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll1_out_even", "cam_cc_pll2_out_main", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_2[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll3", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_EARLY, 3 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_3[] = { "bi_tcxo", "cam_cc_pll2_out_early", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL1_OUT_EVEN, 3 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_4[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll1_out_even", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL1_OUT_EVEN, 3 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_5[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll1_out_even", "cam_cc_pll3", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_6[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL2_OUT_MAIN, 4 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_6[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll2_out_main", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL1_OUT_MAIN, 2 }, { P_CAM_CC_PLL2_OUT_MAIN, 4 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_7[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll1", "cam_cc_pll2_out_main", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL1_OUT_MAIN, 2 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_8[] = { "bi_tcxo", "cam_cc_pll0", "cam_cc_pll1", "core_bi_pll_test_se", }; static const struct parent_map cam_cc_parent_map_9[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_MAIN, 4 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_9[] = { "bi_tcxo", "cam_cc_pll2_out_main", "core_bi_pll_test_se", }; static struct pll_vco fabia_vco[] = { { 249600000, 2000000000, 0 }, }; /* 600MHz configuration */ static const struct alpha_pll_config cam_cc_pll0_config = { .l = 0x1F, .cal_l = 0x22, .alpha = 0x4000, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002067, .test_ctl_val = 0x40000000, .test_ctl_hi_val = 0x00000002, .user_ctl_val = 0x00000101, .user_ctl_hi_val = 0x00004805, }; static struct clk_alpha_pll cam_cc_pll0 = { .offset = 0x0, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0", .parent_names = (const char *[]){ "bi_tcxo" }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .offset = 0x0, .post_div_shift = 8, .post_div_table = post_div_table_cam_cc_pll0_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0_out_even", .parent_names = (const char *[]){ "cam_cc_pll0" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; /* 808MHz configuration */ static const struct alpha_pll_config cam_cc_pll1_config = { .l = 0x2A, .cal_l = 0x2C, .alpha = 0x1555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002067, .test_ctl_val = 0x40000000, .test_ctl_hi_val = 0x00000000, .user_ctl_val = 0x00000101, .user_ctl_hi_val = 0x00004805, }; static struct clk_alpha_pll cam_cc_pll1 = { .offset = 0x1000, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1", .parent_names = (const char *[]){ "bi_tcxo" }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .offset = 0x1000, .post_div_shift = 8, .post_div_table = post_div_table_cam_cc_pll1_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1_out_even", .parent_names = (const char *[]){ "cam_cc_pll1" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, }; /* 1920MHz configuration */ static const struct alpha_pll_config cam_cc_pll2_config = { .l = 0x64, .alpha = 0x0, .post_div_val = 0x3 << 8, .post_div_mask = 0x3 << 8, .aux_output_mask = BIT(1), .main_output_mask = BIT(0), .early_output_mask = BIT(3), .config_ctl_val = 0x20000800, .config_ctl_hi_val = 0x400003d2, .test_ctl_val = 0x04000400, .test_ctl_hi_val = 0x00004000, }; static struct clk_alpha_pll cam_cc_pll2 = { .offset = 0x2000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2", .parent_names = (const char *[]){ "bi_tcxo" }, .num_parents = 1, .ops = &clk_alpha_pll_agera_ops, .vdd_class = &vdd_mx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 1200000000, [VDD_LOWER] = 1800000000, [VDD_LOW] = 2400000000, [VDD_NOMINAL] = 3000000000, [VDD_HIGH] = 3300000000}, }, }, }; static struct clk_fixed_factor cam_cc_pll2_out_early = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_early", .parent_names = (const char *[]){ "cam_cc_pll2" }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, }; static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { .offset = 0x2000, .post_div_shift = 8, .post_div_table = post_div_table_cam_cc_pll2_out_main, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main), .width = 2, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_main", .parent_names = (const char *[]){ "cam_cc_pll2" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ops, }, }; /* 384MHz configuration */ static const struct alpha_pll_config cam_cc_pll3_config = { .l = 0x14, .cal_l = 0x16, .alpha = 0x0, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00002067, .test_ctl_val = 0x40000000, .test_ctl_hi_val = 0x00000002, .user_ctl_val = 0x00000001, .user_ctl_hi_val = 0x00014805, }; static struct clk_alpha_pll cam_cc_pll3 = { .offset = 0x3000, .vco_table = fabia_vco, .num_vco = ARRAY_SIZE(fabia_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3", .parent_names = (const char *[]){ "bi_tcxo" }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 615000000, [VDD_LOW] = 1066000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_bps_clk_src = { .cmd_rcgr = 0x6010, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_bps_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", .parent_names = cam_cc_parent_names_1, .num_parents = 5, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 404000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), { } }; static struct clk_rcg2 cam_cc_cci_0_clk_src = { .cmd_rcgr = 0xf004, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .parent_names = cam_cc_parent_names_0, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 37500000, [VDD_LOW] = 50000000, [VDD_NOMINAL] = 100000000}, }, }; static struct clk_rcg2 cam_cc_cci_1_clk_src = { .cmd_rcgr = 0x10004, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .parent_names = cam_cc_parent_names_0, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 37500000, [VDD_LOW] = 50000000, [VDD_NOMINAL] = 100000000}, }, }; static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { F(150000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), F(384000000, P_CAM_CC_PLL3_OUT_MAIN, 1, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 1.5, 0, 0), { } }; static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .cmd_rcgr = 0x9064, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_names = cam_cc_parent_names_2, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 384000000, [VDD_LOW_L1] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .cmd_rcgr = 0x5004, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000}, }, }; static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .cmd_rcgr = 0x5028, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000}, }, }; static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .cmd_rcgr = 0x504c, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000}, }, }; static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .cmd_rcgr = 0x5070, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000}, }, }; static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { F(100000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .cmd_rcgr = 0x603c, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_4, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_names = cam_cc_parent_names_4, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 100000000, [VDD_LOW] = 200000000, [VDD_LOW_L1] = 300000000, [VDD_NOMINAL] = 404000000}, }, }; static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), F(384000000, P_CAM_CC_PLL3_OUT_MAIN, 1, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_icp_clk_src = { .cmd_rcgr = 0xe014, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_5, .freq_tbl = ftbl_cam_cc_icp_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", .parent_names = cam_cc_parent_names_5, .num_parents = 5, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 384000000, [VDD_LOW] = 404000000, [VDD_LOW_L1] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_0_clk_src = { .cmd_rcgr = 0x9010, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", .parent_names = cam_cc_parent_names_1, .num_parents = 5, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 320000000, [VDD_LOW] = 404000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .cmd_rcgr = 0x903c, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk_src", .parent_names = cam_cc_parent_names_2, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 384000000, [VDD_LOW_L1] = 400000000}, }, }; static struct clk_rcg2 cam_cc_ife_1_clk_src = { .cmd_rcgr = 0xa010, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", .parent_names = cam_cc_parent_names_1, .num_parents = 5, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 320000000, [VDD_LOW] = 404000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .cmd_rcgr = 0xa034, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk_src", .parent_names = cam_cc_parent_names_2, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 384000000, [VDD_LOW_L1] = 400000000}, }, }; static struct clk_rcg2 cam_cc_ife_2_clk_src = { .cmd_rcgr = 0xb00c, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_clk_src", .parent_names = cam_cc_parent_names_1, .num_parents = 5, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 320000000, [VDD_LOW] = 404000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = { .cmd_rcgr = 0xb030, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_csid_clk_src", .parent_names = cam_cc_parent_names_2, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 384000000, [VDD_LOW_L1] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = { F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 1.5, 0, 0), F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .cmd_rcgr = 0xc004, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_6, .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .parent_names = cam_cc_parent_names_6, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 320000000, [VDD_LOW] = 400000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .cmd_rcgr = 0xc024, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", .parent_names = cam_cc_parent_names_2, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 384000000, [VDD_LOW_L1] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { F(240000000, P_CAM_CC_PLL2_OUT_MAIN, 2, 0, 0), F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_MAIN, 2, 0, 0), F(538666667, P_CAM_CC_PLL1_OUT_MAIN, 1.5, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .cmd_rcgr = 0x7010, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_7, .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk_src", .parent_names = cam_cc_parent_names_7, .num_parents = 5, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 240000000, [VDD_LOW] = 320000000, [VDD_LOW_L1] = 404000000, [VDD_NOMINAL] = 538666667, [VDD_HIGH] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { F(66666667, P_CAM_CC_PLL0_OUT_MAIN, 9, 0, 0), F(133333333, P_CAM_CC_PLL0_OUT_MAIN, 4.5, 0, 0), F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_jpeg_clk_src = { .cmd_rcgr = 0xd004, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_jpeg_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", .parent_names = cam_cc_parent_names_1, .num_parents = 5, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 404000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(269333333, P_CAM_CC_PLL1_OUT_MAIN, 3, 0, 0), F(323200000, P_CAM_CC_PLL1_OUT_MAIN, 2.5, 0, 0), F(404000000, P_CAM_CC_PLL1_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 cam_cc_lrme_clk_src = { .cmd_rcgr = 0x11004, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_8, .freq_tbl = ftbl_cam_cc_lrme_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk_src", .parent_names = cam_cc_parent_names_8, .num_parents = 4, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 269333333, [VDD_LOW_L1] = 323200000, [VDD_NOMINAL] = 404000000}, }, }; static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { F(19200000, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 50), F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 4), F(64000000, P_CAM_CC_PLL2_OUT_EARLY, 15, 0, 0), { } }; static struct clk_rcg2 cam_cc_mclk0_clk_src = { .cmd_rcgr = 0x4004, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_3, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_names = cam_cc_parent_names_3, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_mx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 64000000}, }, }; static struct clk_rcg2 cam_cc_mclk1_clk_src = { .cmd_rcgr = 0x4024, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_3, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_names = cam_cc_parent_names_3, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_mx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 64000000}, }, }; static struct clk_rcg2 cam_cc_mclk2_clk_src = { .cmd_rcgr = 0x4044, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_3, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_names = cam_cc_parent_names_3, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_mx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 64000000}, }, }; static struct clk_rcg2 cam_cc_mclk3_clk_src = { .cmd_rcgr = 0x4064, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_3, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_names = cam_cc_parent_names_3, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_mx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 64000000}, }, }; static struct clk_rcg2 cam_cc_mclk4_clk_src = { .cmd_rcgr = 0x4084, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_3, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk_src", .parent_names = cam_cc_parent_names_3, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_mx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 64000000}, }, }; static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { F(80000000, P_CAM_CC_PLL2_OUT_MAIN, 6, 0, 0), { } }; static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .cmd_rcgr = 0x6058, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_9, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .parent_names = cam_cc_parent_names_9, .num_parents = 3, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 80000000}, }, }; static struct clk_branch cam_cc_bps_ahb_clk = { .halt_reg = 0x6070, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6070, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", .parent_names = (const char *[]){ "cam_cc_slow_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_bps_areg_clk = { .halt_reg = 0x6054, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", .parent_names = (const char *[]){ "cam_cc_fast_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_bps_axi_clk = { .halt_reg = 0x6038, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6038, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_bps_clk = { .halt_reg = 0x6028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", .parent_names = (const char *[]){ "cam_cc_bps_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_camnoc_axi_clk = { .halt_reg = 0x13004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_camnoc_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cci_0_clk = { .halt_reg = 0xf01c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xf01c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk", .parent_names = (const char *[]){ "cam_cc_cci_0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cci_1_clk = { .halt_reg = 0x1001c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1001c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk", .parent_names = (const char *[]){ "cam_cc_cci_1_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_core_ahb_clk = { .halt_reg = 0x14010, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x14010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_core_ahb_clk", .parent_names = (const char *[]){ "cam_cc_slow_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ahb_clk = { .halt_reg = 0x12004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x12004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", .parent_names = (const char *[]){ "cam_cc_slow_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi0phytimer_clk = { .halt_reg = 0x501c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x501c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", .parent_names = (const char *[]){ "cam_cc_csi0phytimer_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi1phytimer_clk = { .halt_reg = 0x5040, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", .parent_names = (const char *[]){ "cam_cc_csi1phytimer_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi2phytimer_clk = { .halt_reg = 0x5064, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5064, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", .parent_names = (const char *[]){ "cam_cc_csi2phytimer_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi3phytimer_clk = { .halt_reg = 0x5088, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5088, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", .parent_names = (const char *[]){ "cam_cc_csi3phytimer_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy0_clk = { .halt_reg = 0x5020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy1_clk = { .halt_reg = 0x5044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy2_clk = { .halt_reg = 0x5068, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x5068, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy3_clk = { .halt_reg = 0x508c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x508c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_icp_clk = { .halt_reg = 0xe02c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xe02c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", .parent_names = (const char *[]){ "cam_cc_icp_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_icp_ts_clk = { .halt_reg = 0xe00c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xe00c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_ts_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_axi_clk = { .halt_reg = 0x9080, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9080, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_clk = { .halt_reg = 0x9028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", .parent_names = (const char *[]){ "cam_cc_ife_0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .halt_reg = 0x907c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x907c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_csid_clk = { .halt_reg = 0x9054, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", .parent_names = (const char *[]){ "cam_cc_ife_0_csid_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_dsp_clk = { .halt_reg = 0x9038, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x9038, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", .parent_names = (const char *[]){ "cam_cc_ife_0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_axi_clk = { .halt_reg = 0xa058, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xa058, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_clk = { .halt_reg = 0xa028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xa028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", .parent_names = (const char *[]){ "cam_cc_ife_1_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .halt_reg = 0xa054, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xa054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_csid_clk = { .halt_reg = 0xa04c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xa04c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", .parent_names = (const char *[]){ "cam_cc_ife_1_csid_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_dsp_clk = { .halt_reg = 0xa030, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xa030, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", .parent_names = (const char *[]){ "cam_cc_ife_1_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_axi_clk = { .halt_reg = 0xb054, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xb054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_clk = { .halt_reg = 0xb024, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xb024, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_clk", .parent_names = (const char *[]){ "cam_cc_ife_2_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_cphy_rx_clk = { .halt_reg = 0xb050, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xb050, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_cphy_rx_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_csid_clk = { .halt_reg = 0xb048, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xb048, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_csid_clk", .parent_names = (const char *[]){ "cam_cc_ife_2_csid_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_dsp_clk = { .halt_reg = 0xb02c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xb02c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_dsp_clk", .parent_names = (const char *[]){ "cam_cc_ife_2_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_clk = { .halt_reg = 0xc01c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xc01c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", .parent_names = (const char *[]){ "cam_cc_ife_lite_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .halt_reg = 0xc044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xc044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", .parent_names = (const char *[]){ "cam_cc_cphy_rx_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_csid_clk = { .halt_reg = 0xc03c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xc03c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", .parent_names = (const char *[]){ "cam_cc_ife_lite_csid_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_0_ahb_clk = { .halt_reg = 0x7040, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x7040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", .parent_names = (const char *[]){ "cam_cc_slow_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_0_areg_clk = { .halt_reg = 0x703c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x703c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", .parent_names = (const char *[]){ "cam_cc_fast_ahb_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_0_axi_clk = { .halt_reg = 0x7038, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x7038, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_axi_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_0_clk = { .halt_reg = 0x7028, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x7028, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", .parent_names = (const char *[]){ "cam_cc_ipe_0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_jpeg_clk = { .halt_reg = 0xd01c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xd01c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", .parent_names = (const char *[]){ "cam_cc_jpeg_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_lrme_clk = { .halt_reg = 0x1101c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1101c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", .parent_names = (const char *[]){ "cam_cc_lrme_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk0_clk = { .halt_reg = 0x401c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x401c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", .parent_names = (const char *[]){ "cam_cc_mclk0_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk1_clk = { .halt_reg = 0x403c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x403c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", .parent_names = (const char *[]){ "cam_cc_mclk1_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk2_clk = { .halt_reg = 0x405c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x405c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", .parent_names = (const char *[]){ "cam_cc_mclk2_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk3_clk = { .halt_reg = 0x407c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x407c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", .parent_names = (const char *[]){ "cam_cc_mclk3_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk4_clk = { .halt_reg = 0x409c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x409c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk", .parent_names = (const char *[]){ "cam_cc_mclk4_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_soc_ahb_clk = { .halt_reg = 0x1400c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1400c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_soc_ahb_clk", .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sys_tmr_clk = { .halt_reg = 0xe034, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0xe034, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sys_tmr_clk", .ops = &clk_branch2_ops, }, }, }; struct clk_hw *cam_cc_lagoon_hws[] = { [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, }; static struct clk_regmap *cam_cc_lagoon_clocks[] = { [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, [CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr, [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, [CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr, [CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr, [CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr, [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, [CAM_CC_PLL0] = &cam_cc_pll0.clkr, [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, [CAM_CC_PLL1] = &cam_cc_pll1.clkr, [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, [CAM_CC_PLL2] = &cam_cc_pll2.clkr, [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr, [CAM_CC_PLL3] = &cam_cc_pll3.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, }; static const struct regmap_config cam_cc_lagoon_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x15700, .fast_io = true, }; static const struct qcom_cc_desc cam_cc_lagoon_desc = { .config = &cam_cc_lagoon_regmap_config, .hwclks = cam_cc_lagoon_hws, .num_hwclks = ARRAY_SIZE(cam_cc_lagoon_hws), .clks = cam_cc_lagoon_clocks, .num_clks = ARRAY_SIZE(cam_cc_lagoon_clocks), }; static const struct of_device_id cam_cc_lagoon_match_table[] = { { .compatible = "qcom,lagoon-camcc" }, { } }; MODULE_DEVICE_TABLE(of, cam_cc_lagoon_match_table); static int cam_cc_lagoon_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); if (IS_ERR(vdd_cx.regulator[0])) { if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n"); return PTR_ERR(vdd_cx.regulator[0]); } vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx"); if (IS_ERR(vdd_mx.regulator[0])) { if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n"); return PTR_ERR(vdd_mx.regulator[0]); } regmap = qcom_cc_map(pdev, &cam_cc_lagoon_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); ret = qcom_cc_really_probe(pdev, &cam_cc_lagoon_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered CAM CC clocks\n"); return 0; } static struct platform_driver cam_cc_lagoon_driver = { .probe = cam_cc_lagoon_probe, .driver = { .name = "lagoon-camcc", .of_match_table = cam_cc_lagoon_match_table, }, }; static int __init cam_cc_lagoon_init(void) { return platform_driver_register(&cam_cc_lagoon_driver); } subsys_initcall(cam_cc_lagoon_init); static void __exit cam_cc_lagoon_exit(void) { platform_driver_unregister(&cam_cc_lagoon_driver); } module_exit(cam_cc_lagoon_exit); MODULE_DESCRIPTION("QTI CAM_CC LAGOON Driver"); MODULE_LICENSE("GPL v2");