/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */

#ifndef __MDSS_12NM_PLL_CLK_H
#define __MDSS_12NM_PLL_CLK_H

/* DSI PLL clocks */
#define VCO_CLK_0		0
#define POST_DIV1_0_CLK		1
#define POST_DIV2_0_CLK		2
#define POST_DIV4_0_CLK		3
#define POST_DIV8_0_CLK		4
#define POST_DIV16_0_CLK	5
#define POST_DIV32_0_CLK	6
#define POST_DIV_MUX_0_CLK	7
#define GP_DIV1_0_CLK		8
#define GP_DIV2_0_CLK		9
#define GP_DIV4_0_CLK		10
#define GP_DIV8_0_CLK		11
#define GP_DIV16_0_CLK		12
#define GP_DIV32_0_CLK		13
#define GP_DIV_MUX_0_CLK	14
#define PCLK_SRC_MUX_0_CLK	15
#define BYTE_CLK_SRC_0_CLK	16

#define VCO_CLK_1		17
#define POST_DIV1_1_CLK		18
#define POST_DIV2_1_CLK		19
#define POST_DIV4_1_CLK		20
#define POST_DIV8_1_CLK		21
#define POST_DIV16_1_CLK	22
#define POST_DIV32_1_CLK	23
#define POST_DIV_MUX_1_CLK	24
#define GP_DIV1_1_CLK		25
#define GP_DIV2_1_CLK		26
#define GP_DIV4_1_CLK		27
#define GP_DIV8_1_CLK		28
#define GP_DIV16_1_CLK		29
#define GP_DIV32_1_CLK		30
#define GP_DIV_MUX_1_CLK	31
#define PCLK_SRC_MUX_1_CLK	32
#define BYTE_CLK_SRC_1_CLK	33

#endif