#ifndef _HAPTIC_HV_REG_H_ #define _HAPTIC_HV_REG_H_ /********************************************************* * * AW869X Register List * *********************************************************/ #define AW869X_REG_SYSST (0x01) #define AW869X_REG_SYSINT (0x02) #define AW869X_REG_SYSINTM (0x03) #define AW869X_REG_SYSCTRL (0x04) #define AW869X_REG_GO (0x05) #define AW869X_REG_RTP_DATA (0x06) #define AW869X_REG_WAVSEQ1 (0x07) #define AW869X_REG_WAVSEQ2 (0x08) #define AW869X_REG_WAVSEQ3 (0x09) #define AW869X_REG_WAVSEQ4 (0x0a) #define AW869X_REG_WAVSEQ5 (0x0b) #define AW869X_REG_WAVSEQ6 (0x0c) #define AW869X_REG_WAVSEQ7 (0x0d) #define AW869X_REG_WAVSEQ8 (0x0e) #define AW869X_REG_WAVLOOP1 (0x0f) #define AW869X_REG_WAVLOOP2 (0x10) #define AW869X_REG_WAVLOOP3 (0x11) #define AW869X_REG_WAVLOOP4 (0x12) #define AW869X_REG_TRG1_WAV_P (0x14) #define AW869X_REG_TRG2_WAV_P (0x15) #define AW869X_REG_TRG3_WAV_P (0x16) #define AW869X_REG_TRG1_WAV_N (0x17) #define AW869X_REG_TRG2_WAV_N (0x18) #define AW869X_REG_TRG3_WAV_N (0x19) #define AW869X_REG_TRG_CFG1 (0x1b) #define AW869X_REG_TRG_CFG2 (0x1c) #define AW869X_REG_DBGCTRL (0x20) #define AW869X_REG_BASE_ADDRH (0x21) #define AW869X_REG_BASE_ADDRL (0x22) #define AW869X_REG_FIFO_AEH (0x23) #define AW869X_REG_FIFO_AEL (0x24) #define AW869X_REG_FIFO_AFH (0x25) #define AW869X_REG_FIFO_AFL (0x26) #define AW869X_REG_DATCTRL (0x2b) #define AW869X_REG_PWMPRC (0x2d) #define AW869X_REG_PWMDBG (0x2e) #define AW869X_REG_DBGSTAT (0x30) #define AW869X_REG_BSTDBG1 (0x31) #define AW869X_REG_BSTDBG2 (0x32) #define AW869X_REG_BSTDBG3 (0x33) #define AW869X_REG_BSTCFG (0x34) #define AW869X_REG_ANADBG (0x35) #define AW869X_REG_ANACTRL (0x36) #define AW869X_REG_DATDBG (0x39) #define AW869X_REG_BSTDBG4 (0x3a) #define AW869X_REG_PRLVL (0x3e) #define AW869X_REG_PRTIME (0x3f) #define AW869X_REG_RAMADDRH (0x40) #define AW869X_REG_RAMADDRL (0x41) #define AW869X_REG_RAMDATA (0x42) #define AW869X_REG_GLB_STATE (0x46) #define AW869X_REG_BST_AUTO (0x47) #define AW869X_REG_CONT_CTRL (0x48) #define AW869X_REG_F_PRE_H (0x49) #define AW869X_REG_F_PRE_L (0x4a) #define AW869X_REG_TD_H (0x4b) #define AW869X_REG_TD_L (0x4c) #define AW869X_REG_TSET (0x4d) #define AW869X_REG_TRIM_LRA (0x5b) #define AW869X_REG_R_SPARE (0x5d) #define AW869X_REG_D2SCFG (0x5e) #define AW869X_REG_DETCTRL (0x5f) #define AW869X_REG_RLDET (0x60) #define AW869X_REG_VBATDET (0x62) #define AW869X_REG_ADCTEST (0x66) #define AW869X_REG_F_LRA_F0_H (0x68) #define AW869X_REG_F_LRA_F0_L (0x69) #define AW869X_REG_F_LRA_CONT_H (0x6a) #define AW869X_REG_F_LRA_CONT_L (0x6b) #define AW869X_REG_WAIT_VOL_MP (0x6d) #define AW869X_REG_WAIT_VOL_MN (0x6f) #define AW869X_REG_ZC_THRSH_H (0x72) #define AW869X_REG_ZC_THRSH_L (0x73) #define AW869X_REG_BEMF_VTHH_H (0x74) #define AW869X_REG_BEMF_VTHH_L (0x75) #define AW869X_REG_BEMF_VTHL_H (0x76) #define AW869X_REG_BEMF_VTHL_L (0x77) #define AW869X_REG_BEMF_NUM (0x78) #define AW869X_REG_TIME_NZC (0x7a) #define AW869X_REG_DRV_LVL (0x7b) #define AW869X_REG_DRV_LVL_OV (0x7c) #define AW869X_REG_NUM_F0_1 (0x7d) #define AW869X_REG_NUM_F0_2 (0x7e) #define AW869X_REG_NUM_F0_3 (0x7f) /********************************************************* * * AW8692X Register List * *********************************************************/ #define AW8692X_REG_RSTCFG (0x00) #define AW8692X_REG_SYSST (0x01) #define AW8692X_REG_SYSINT (0x02) #define AW8692X_REG_SYSINTM (0x03) #define AW8692X_REG_SYSST2 (0x04) #define AW8692X_REG_SYSER (0x05) #define AW8692X_REG_PLAYCFG1 (0x06) #define AW8692X_REG_PLAYCFG2 (0x07) #define AW8692X_REG_PLAYCFG3 (0x08) #define AW8692X_REG_PLAYCFG4 (0x09) #define AW8692X_REG_WAVCFG1 (0x0A) #define AW8692X_REG_WAVCFG2 (0x0B) #define AW8692X_REG_WAVCFG3 (0x0C) #define AW8692X_REG_WAVCFG4 (0x0D) #define AW8692X_REG_WAVCFG5 (0x0E) #define AW8692X_REG_WAVCFG6 (0x0F) #define AW8692X_REG_WAVCFG7 (0x10) #define AW8692X_REG_WAVCFG8 (0x11) #define AW8692X_REG_WAVCFG9 (0x12) #define AW8692X_REG_WAVCFG10 (0x13) #define AW8692X_REG_WAVCFG11 (0x14) #define AW8692X_REG_WAVCFG12 (0x15) #define AW8692X_REG_WAVCFG13 (0x16) #define AW8692X_REG_CONTCFG1 (0x18) #define AW8692X_REG_CONTCFG2 (0x19) #define AW8692X_REG_CONTCFG3 (0x1A) #define AW8692X_REG_CONTCFG4 (0x1B) #define AW8692X_REG_CONTCFG5 (0x1C) #define AW8692X_REG_CONTCFG6 (0x1D) #define AW8692X_REG_CONTCFG7 (0x1E) #define AW8692X_REG_CONTCFG8 (0x1F) #define AW8692X_REG_CONTCFG9 (0x20) #define AW8692X_REG_CONTCFG10 (0x21) #define AW8692X_REG_CONTCFG11 (0x22) #define AW8692X_REG_CONTCFG12 (0x23) #define AW8692X_REG_CONTCFG13 (0x24) #define AW8692X_REG_CONTCFG14 (0x25) #define AW8692X_REG_CONTCFG15 (0x26) #define AW8692X_REG_CONTCFG16 (0x27) #define AW8692X_REG_CONTCFG17 (0x28) #define AW8692X_REG_CONTCFG18 (0x29) #define AW8692X_REG_CONTCFG19 (0x2A) #define AW8692X_REG_CONTCFG20 (0x2B) #define AW8692X_REG_CONTCFG21 (0x2C) #define AW8692X_REG_RTPCFG1 (0x2D) #define AW8692X_REG_RTPCFG2 (0x2E) #define AW8692X_REG_RTPCFG3 (0x2F) #define AW8692X_REG_RTPCFG4 (0x30) #define AW8692X_REG_RTPCFG5 (0x31) #define AW8692X_REG_RTPDATA (0X32) #define AW8692X_REG_TRGCFG1 (0x33) #define AW8692X_REG_TRGCFG2 (0x34) #define AW8692X_REG_TRGCFG3 (0x35) #define AW8692X_REG_TRGCFG4 (0x36) #define AW8692X_REG_TRGCFG5 (0x37) #define AW8692X_REG_TRGCFG6 (0x38) #define AW8692X_REG_TRGCFG7 (0x39) #define AW8692X_REG_TRGCFG8 (0x3A) #define AW8692X_REG_GLBCFG1 (0x3B) #define AW8692X_REG_GLBCFG2 (0x3C) #define AW8692X_REG_GLBCFG3 (0x3D) #define AW8692X_REG_GLBCFG4 (0x3E) #define AW8692X_REG_GLBRD5 (0x3F) #define AW8692X_REG_RAMADDRH (0x40) #define AW8692X_REG_RAMADDRL (0x41) #define AW8692X_REG_RAMDATA (0x42) #define AW8692X_REG_SYSCTRL1 (0x43) #define AW8692X_REG_SYSCTRL2 (0x44) #define AW8692X_REG_SYSCTRL3 (0x45) #define AW8692X_REG_SYSCTRL4 (0x46) #define AW8692X_REG_SYSCTRL5 (0x47) #define AW8692X_REG_PWMCFG1 (0x48) #define AW8692X_REG_PWMCFG2 (0x49) #define AW8692X_REG_PWMCFG3 (0x4A) #define AW8692X_REG_PWMCFG4 (0x4B) #define AW8692X_REG_VBATCTRL (0x4C) #define AW8692X_REG_DETCFG1 (0x4D) #define AW8692X_REG_DETCFG2 (0x4E) #define AW8692X_REG_DETRD1 (0x4F) #define AW8692X_REG_DETRD2 (0x50) #define AW8692X_REG_DETRD3 (0x51) #define AW8692X_REG_TRIMCFG1 (0x52) #define AW8692X_REG_TRIMCFG2 (0x53) #define AW8692X_REG_TRIMCFG3 (0x54) #define AW8692X_REG_TRIMCFG4 (0x55) #define AW8692X_REG_IDH (0x57) #define AW8692X_REG_IDL (0x58) #define AW8692X_REG_AUTOSIN1 (0x59) #define AW8692X_REG_AUTOSIN2 (0x5A) #define AW8692X_REG_TMCFG (0x5B) #define AW8692X_REG_EFCFG6 (0x61) #define AW8692X_REG_ANACFG12 (0x71) #define AW8692X_REG_ANACFG13 (0x72) #define AW8692X_REG_ANACFG15 (0x74) #define AW8692X_REG_ANACFG16 (0x75) #define AW8692X_REG_ANACFG20 (0x79) /********************************************************* * * Register Access * *********************************************************/ #define REG_NONE_ACCESS (0) #define REG_RD_ACCESS (1 << 0) #define REG_WR_ACCESS (1 << 1) #define AW_HAPTIC_REG_MAX (0xff) /********************************************************* * * COMMON Register Detail * *********************************************************/ /* SYSST: reg0x01 */ #define AW_BIT_SYSST_FF_AES (1<<4) #define AW_BIT_SYSST_FF_AFS (1<<3) #define AW_BIT_SYSST_OCDS (1<<2) #define AW_BIT_SYSST_OTS (1<<1) #define AW_BIT_SYSST_DONES (1<<0) /* SYSINT: reg0x02 */ #define AW_BIT_SYSINT_FF_AEI (1<<4) #define AW_BIT_SYSINT_FF_AFI (1<<3) #define AW_BIT_SYSINT_OCDI (1<<2) #define AW_BIT_SYSINT_OTI (1<<1) #define AW_BIT_SYSINT_DONEI (1<<0) /********************************************************* * * AW869X Register Detail * *********************************************************/ /* SYSST: reg0x01 */ #define AW869X_BIT_SYSST_BSTERRS (1<<7) #define AW869X_BIT_SYSST_OVS (1<<6) #define AW869X_BIT_SYSST_UVLS (1<<5) #define AW869X_BIT_SYSST_FF_AES (1<<4) #define AW869X_BIT_SYSST_FF_AFS (1<<3) #define AW869X_BIT_SYSST_OCDS (1<<2) #define AW869X_BIT_SYSST_OTS (1<<1) #define AW869X_BIT_SYSST_DONES (1<<0) /* SYSINT: reg0x02 */ #define AW869X_BIT_SYSINT_BSTERRI (1<<7) #define AW869X_BIT_SYSINT_OVI (1<<6) #define AW869X_BIT_SYSINT_UVLI (1<<5) #define AW869X_BIT_SYSINT_FF_AEI (1<<4) #define AW869X_BIT_SYSINT_FF_AFI (1<<3) #define AW869X_BIT_SYSINT_OCDI (1<<2) #define AW869X_BIT_SYSINT_OTI (1<<1) #define AW869X_BIT_SYSINT_DONEI (1<<0) /* SYSINTM: reg0x03 */ #define AW869X_BIT_SYSINTM_BSTERR_MASK (~(1<<7)) #define AW869X_BIT_SYSINTM_BSTERR_OFF (1<<7) #define AW869X_BIT_SYSINTM_BSTERR_EN (0<<7) #define AW869X_BIT_SYSINTM_OV_MASK (~(1<<6)) #define AW869X_BIT_SYSINTM_OV_OFF (1<<6) #define AW869X_BIT_SYSINTM_OV_EN (0<<6) #define AW869X_BIT_SYSINTM_UVLO_MASK (~(1<<5)) #define AW869X_BIT_SYSINTM_UVLO_OFF (1<<5) #define AW869X_BIT_SYSINTM_UVLO_EN (0<<5) #define AW869X_BIT_SYSINTM_FF_AE_MASK (~(1<<4)) #define AW869X_BIT_SYSINTM_FF_AE_OFF (1<<4) #define AW869X_BIT_SYSINTM_FF_AE_EN (0<<4) #define AW869X_BIT_SYSINTM_FF_AF_MASK (~(1<<3)) #define AW869X_BIT_SYSINTM_FF_AF_OFF (1<<3) #define AW869X_BIT_SYSINTM_FF_AF_EN (0<<3) #define AW869X_BIT_SYSINTM_OCD_MASK (~(1<<2)) #define AW869X_BIT_SYSINTM_OCD_OFF (1<<2) #define AW869X_BIT_SYSINTM_OCD_EN (0<<2) #define AW869X_BIT_SYSINTM_OT_MASK (~(1<<1)) #define AW869X_BIT_SYSINTM_OT_OFF (1<<1) #define AW869X_BIT_SYSINTM_OT_EN (0<<1) #define AW869X_BIT_SYSINTM_DONE_MASK (~(1<<0)) #define AW869X_BIT_SYSINTM_DONE_OFF (1<<0) #define AW869X_BIT_SYSINTM_DONE_EN (0<<0) /* SYSCTRL: reg0x04 */ #define AW869X_BIT_SYSCTRL_WAVDAT_MODE_MASK (~(3<<6)) #define AW869X_BIT_SYSCTRL_WAVDAT_MODE_4X (3<<6) #define AW869X_BIT_SYSCTRL_WAVDAT_MODE_2X (0<<6) #define AW869X_BIT_SYSCTRL_WAVDAT_MODE_1X (1<<6) #define AW869X_BIT_SYSCTRL_RAMINIT_MASK (~(1<<5)) #define AW869X_BIT_SYSCTRL_RAMINIT_EN (1<<5) #define AW869X_BIT_SYSCTRL_RAMINIT_OFF (0<<5) #define AW869X_BIT_SYSCTRL_PLAY_MODE_MASK (~(3<<2)) #define AW869X_BIT_SYSCTRL_PLAY_MODE_CONT (2<<2) #define AW869X_BIT_SYSCTRL_PLAY_MODE_RTP (1<<2) #define AW869X_BIT_SYSCTRL_PLAY_MODE_RAM (0<<2) #define AW869X_BIT_SYSCTRL_BST_MODE_MASK (~(1<<1)) #define AW869X_BIT_SYSCTRL_BST_MODE_BOOST (1<<1) #define AW869X_BIT_SYSCTRL_BST_MODE_BYPASS (0<<1) #define AW869X_BIT_SYSCTRL_WORK_MODE_MASK (~(1<<0)) #define AW869X_BIT_SYSCTRL_STANDBY (1<<0) #define AW869X_BIT_SYSCTRL_ACTIVE (0<<0) /* GO: reg0x05 */ #define AW869X_BIT_GO_MASK (~(1<<0)) #define AW869X_BIT_GO_ENABLE (1<<0) #define AW869X_BIT_GO_DISABLE (0<<0) /* WAVSEQ1: reg0x07 */ #define AW869X_BIT_WAVSEQ1_WAIT (1<<7) #define AW869X_BIT_WAVSEQ1_WAV_FRM_SEQ1_MASK (~(127<<0)) /* WAVSEQ2: reg0x08 */ #define AW869X_BIT_WAVSEQ2_WAIT (1<<7) #define AW869X_BIT_WAVSEQ2_WAV_FRM_SEQ2_MASK (~(127<<0)) /* WAVSEQ3: reg0x09 */ #define AW869X_BIT_WAVSEQ3_WAIT (1<<7) #define AW869X_BIT_WAVSEQ3_WAV_FRM_SEQ3_MASK (~(127<<0)) /* WAVSEQ4: reg0x0a */ #define AW869X_BIT_WAVSEQ4_WAIT (1<<7) #define AW869X_BIT_WAVSEQ4_WAV_FRM_SEQ4_MASK (~(127<<0)) /* WAVSEQ5: reg0x0b */ #define AW869X_BIT_WAVSEQ5_WAIT (1<<7) #define AW869X_BIT_WAVSEQ5_WAV_FRM_SEQ5_MASK (~(127<<0)) /* WAVSEQ6: reg0x0c */ #define AW869X_BIT_WAVSEQ6_WAIT (1<<7) #define AW869X_BIT_WAVSEQ6_WAV_FRM_SEQ6_MASK (~(127<<0)) /* WAVSEQ7: reg0x0d */ #define AW869X_BIT_WAVSEQ7_WAIT (1<<7) #define AW869X_BIT_WAVSEQ7_WAV_FRM_SEQ7_MASK (~(127<<0)) /* WAVSEQ8: reg0x0e */ #define AW869X_BIT_WAVSEQ8_WAIT (1<<7) #define AW869X_BIT_WAVSEQ8_WAV_FRM_SEQ8_MASK (~(127<<0)) /* WAVLOOP: */ #define AW869X_BIT_WAVLOOP_SEQN_MASK (~(15<<4)) #define AW869X_BIT_WAVLOOP_SEQNP1_MASK (~(15<<0)) #define AW869X_BIT_WAVLOOP_INIFINITELY (15<<0) /* WAVLOOP1: reg0x0f */ #define AW869X_BIT_WAVLOOP1_SEQ1_MASK (~(15<<4)) #define AW869X_BIT_WAVLOOP1_SEQ2_MASK (~(15<<0)) /* WAVLOOP2: reg0x10 */ #define AW869X_BIT_WAVLOOP2_SEQ3_MASK (~(15<<4)) #define AW869X_BIT_WAVLOOP2_SEQ4_MASK (~(15<<0)) /* WAVLOOP3: reg0x11 */ #define AW869X_BIT_WAVLOOP3_SEQ5_MASK (~(15<<4)) #define AW869X_BIT_WAVLOOP3_SEQ6_MASK (~(15<<0)) /* WAVLOOP4: reg0x12 */ #define AW869X_BIT_WAVLOOP4_SEQ7_MASK (~(15<<4)) #define AW869X_BIT_WAVLOOP4_SEQ8_MASK (~(15<<0)) /* TRGCFG1: reg0x1b */ #define AW869X_BIT_TRGCFG1_TRG3_POLAR_MASK (~(1<<5)) #define AW869X_BIT_TRGCFG1_TRG3_POLAR_NEG (1<<5) #define AW869X_BIT_TRGCFG1_TRG3_POLAR_POS (0<<5) #define AW869X_BIT_TRGCFG1_TRG3_EDGE_MASK (~(1<<4)) #define AW869X_BIT_TRGCFG1_TRG3_EDGE_POS (1<<4) #define AW869X_BIT_TRGCFG1_TRG3_EDGE_POS_NEG (0<<4) #define AW869X_BIT_TRGCFG1_TRG2_POLAR_MASK (~(1<<3)) #define AW869X_BIT_TRGCFG1_TRG2_POLAR_NEG (1<<3) #define AW869X_BIT_TRGCFG1_TRG2_POLAR_POS (0<<3) #define AW869X_BIT_TRGCFG1_TRG2_EDGE_MASK (~(1<<2)) #define AW869X_BIT_TRGCFG1_TRG2_EDGE_POS (1<<2) #define AW869X_BIT_TRGCFG1_TRG2_EDGE_POS_NEG (0<<2) #define AW869X_BIT_TRGCFG1_TRG1_POLAR_MASK (~(1<<1)) #define AW869X_BIT_TRGCFG1_TRG1_POLAR_NEG (1<<1) #define AW869X_BIT_TRGCFG1_TRG1_POLAR_POS (0<<1) #define AW869X_BIT_TRGCFG1_TRG1_EDGE_MASK (~(1<<0)) #define AW869X_BIT_TRGCFG1_TRG1_EDGE_POS (1<<0) #define AW869X_BIT_TRGCFG1_TRG1_EDGE_POS_NEG (0<<0) /* TRGCFG2: reg0x1c */ #define AW869X_BIT_TRGCFG2_TRG3_ENABLE_MASK (~(1<<2)) #define AW869X_BIT_TRGCFG2_TRG3_ENABLE (1<<2) #define AW869X_BIT_TRGCFG2_TRG3_DISABLE (0<<2) #define AW869X_BIT_TRGCFG2_TRG2_ENABLE_MASK (~(1<<1)) #define AW869X_BIT_TRGCFG2_TRG2_ENABLE (1<<1) #define AW869X_BIT_TRGCFG2_TRG2_DISABLE (0<<1) #define AW869X_BIT_TRGCFG2_TRG1_ENABLE_MASK (~(1<<0)) #define AW869X_BIT_TRGCFG2_TRG1_ENABLE (1<<0) #define AW869X_BIT_TRGCFG2_TRG1_DISABLE (0<<0) /* DBGCTRL: reg0x20 */ #define AW869X_BIT_DBGCTRL_INT_EDGE_MODE_MASK (~(1<<3)) #define AW869X_BIT_DBGCTRL_INT_EDGE_MODE_POS (1<<3) #define AW869X_BIT_DBGCTRL_INT_EDGE_MODE_BOTH (0<<3) #define AW869X_BIT_DBGCTRL_INT_MODE_MASK (~(1<<2)) #define AW869X_BIT_DBGCTRL_INT_MODE_EDGE (1<<2) #define AW869X_BIT_DBGCTRL_INT_MODE_LEVEL (0<<2) /* DATCTRL: reg0x2b */ #define AW869X_BIT_DATCTRL_FC_MASK (~(1<<6)) #define AW869X_BIT_DATCTRL_FC_1000HZ (3<<6) #define AW869X_BIT_DATCTRL_FC_800HZ (3<<6) #define AW869X_BIT_DATCTRL_FC_600HZ (1<<6) #define AW869X_BIT_DATCTRL_FC_400HZ (0<<6) #define AW869X_BIT_DATCTRL_LPF_ENABLE_MASK (~(1<<5)) #define AW869X_BIT_DATCTRL_LPF_ENABLE (1<<5) #define AW869X_BIT_DATCTRL_LPF_DISABLE (0<<5) #define AW869X_BIT_DATCTRL_WAKEMODE_ENABLE_MASK (~(1<<0)) #define AW869X_BIT_DATCTRL_WAKEMODE_ENABLE (1<<0) #define AW869X_BIT_DATCTRL_WAKEMODE_DISABLE (0<<0) /* PWMPRC: reg0x2d */ #define AW869X_BIT_PWMPRC_PRC_MASK (~(1<<7)) #define AW869X_BIT_PWMPRC_PRC_ENABLE (1<<7) #define AW869X_BIT_PWMPRC_PRC_DISABLE (0<<7) #define AW869X_BIT_PWMPRC_PRCTIME_MASK (~(0x7f<<0)) /* PWMDBG: reg0x2e */ #define AW869X_BIT_PWMDBG_PWM_MODE_MASK (~(3<<5)) #define AW869X_BIT_PWMDBG_PWM_12K (3<<5) #define AW869X_BIT_PWMDBG_PWM_24K (2<<5) #define AW869X_BIT_PWMDBG_PWM_48K (0<<5) /* DBGST: reg0x30 */ #define AW869X_BIT_DBGSTAT_FF_EMPTY (1<<0) /* BSTCFG: reg0x34 */ #define AW869X_BIT_BSTCFG_PEAKCUR_MASK (~(7<<0)) #define AW869X_BIT_BSTCFG_PEAKCUR_4A (7<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_3P75A (6<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_3P5A (5<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_3A (4<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_2P5A (3<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_2P25A (2<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_2A (1<<0) #define AW869X_BIT_BSTCFG_PEAKCUR_1P75A (0<<0) /* ANADBG: reg0x35 */ #define AW869X_BIT_ANADBG_IOC_MASK (~(3<<2)) #define AW869X_BIT_ANADBG_IOC_4P65A (3<<2) #define AW869X_BIT_ANADBG_IOC_4P15A (2<<2) #define AW869X_BIT_ANADBG_IOC_3P65A (1<<2) #define AW869X_BIT_ANADBG_IOC_3P15A (0<<2) /* ANACTRL: reg0x36 */ #define AW869X_BIT_ANACTRL_LRA_SRC_MASK (~(1<<5)) #define AW869X_BIT_ANACTRL_LRA_SRC_REG (1<<5) #define AW869X_BIT_ANACTRL_LRA_SRC_EFUSE (0<<5) #define AW869X_BIT_ANACTRL_HD_PD_MASK (~(1<<3)) #define AW869X_BIT_ANACTRL_HD_PD_EN (1<<3) #define AW869X_BIT_ANACTRL_HD_HZ_EN (0<<3) /* BSTDBG4: reg0x3a */ #define AW869X_BIT_BSTDBG4_BSTVOL_MASK (~(31<<1)) /* PRLVL: reg0x3e */ #define AW869X_BIT_PRLVL_PR_MASK (~(1<<7)) #define AW869X_BIT_PRLVL_PR_ENABLE (1<<7) #define AW869X_BIT_PRLVL_PR_DISABLE (0<<7) #define AW869X_BIT_PRLVL_PRLVL_MASK (~(0x7f<<0)) /*PRTIME: reg0x3f */ #define AW869X_BIT_PRTIME_PRTIME_MASK (~(0xff<<0)) /* GLB_STATE: reg 0x3F */ /* GLB_STATE [3:0] */ #define AW869X_BIT_GLB_STATE_STANDBY (0<<0) /* BST_AUTO: reg0x47 */ #define AW869X_BIT_BST_AUTO_BST_AUTOSW_MASK (~(1<<2)) #define AW869X_BIT_BST_AUTO_BST_AUTOMATIC_BOOST (1<<2) #define AW869X_BIT_BST_AUTO_BST_MANUAL_BOOST (0<<2) #define AW869X_BIT_BST_AUTO_BST_RTP_MASK (~(1<<1)) #define AW869X_BIT_BST_AUTO_BST_RTP_ENABLE (1<<1) #define AW869X_BIT_BST_AUTO_BST_RTP_DISABLE (0<<1) #define AW869X_BIT_BST_AUTO_BST_RAM_MASK (~(1<<0)) #define AW869X_BIT_BST_AUTO_BST_RAM_ENABLE (1<<0) #define AW869X_BIT_BST_AUTO_BST_RAM_DISABLE (0<<0) /* CONT_CTRL: reg0x48 */ #define AW869X_BIT_CONT_CTRL_ZC_DETEC_MASK (~(1<<7)) #define AW869X_BIT_CONT_CTRL_ZC_DETEC_ENABLE (1<<7) #define AW869X_BIT_CONT_CTRL_ZC_DETEC_DISABLE (0<<7) #define AW869X_BIT_CONT_CTRL_WAIT_PERIOD_MASK (~(3<<5)) #define AW869X_BIT_CONT_CTRL_WAIT_8PERIOD (3<<5) #define AW869X_BIT_CONT_CTRL_WAIT_4PERIOD (2<<5) #define AW869X_BIT_CONT_CTRL_WAIT_2PERIOD (1<<5) #define AW869X_BIT_CONT_CTRL_WAIT_1PERIOD (0<<5) #define AW869X_BIT_CONT_CTRL_MODE_MASK (~(1<<4)) #define AW869X_BIT_CONT_CTRL_BY_DRV_TIME (1<<4) #define AW869X_BIT_CONT_CTRL_BY_GO_SIGNAL (0<<4) #define AW869X_BIT_CONT_CTRL_EN_CLOSE_MASK (~(1<<3)) #define AW869X_BIT_CONT_CTRL_CLOSE_PLAYBACK (1<<3) #define AW869X_BIT_CONT_CTRL_OPEN_PLAYBACK (0<<3) #define AW869X_BIT_CONT_CTRL_F0_DETECT_MASK (~(1<<2)) #define AW869X_BIT_CONT_CTRL_F0_DETECT_ENABLE (1<<2) #define AW869X_BIT_CONT_CTRL_F0_DETECT_DISABLE (0<<2) #define AW869X_BIT_CONT_CTRL_O2C_MASK (~(1<<1)) #define AW869X_BIT_CONT_CTRL_O2C_ENABLE (1<<1) #define AW869X_BIT_CONT_CTRL_O2C_DISABLE (0<<1) #define AW869X_BIT_CONT_CTRL_AUTO_BRK_MASK (~(1<<0)) #define AW869X_BIT_CONT_CTRL_AUTO_BRK_ENABLE (1<<0) #define AW869X_BIT_CONT_CTRL_AUTO_BRK_DISABLE (0<<0) /* D2SCFG: reg0x5e */ #define AW869X_BIT_D2SCFG_CLK_ADC_MASK (~(7<<5)) #define AW869X_BIT_D2SCFG_CLK_ASC_0P09375MHZ (7<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_0P1875MHZ (6<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_0P375MHZ (5<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_0P75MHZ (4<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_1P5MHZ (3<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_3MHZ (2<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_6MHZ (1<<5) #define AW869X_BIT_D2SCFG_CLK_ASC_12MHZ (0<<5) #define AW869X_BIT_D2SCFG_D2S_GAIN_MASK (~(7<<0)) #define AW869X_BIT_D2SCFG_D2S_GAIN_1 (0<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_2 (1<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_4 (2<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_5 (3<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_8 (4<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_10 (5<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_20 (6<<0) #define AW869X_BIT_D2SCFG_D2S_GAIN_40 (7<<0) /* DETCTRL: reg0x5f */ #define AW869X_BIT_DETCTRL_RL_OS_MASK (~(1<<6)) #define AW869X_BIT_DETCTRL_RL_DETECT (1<<6) #define AW869X_BIT_DETCTRL_OS_DETECT (0<<6) #define AW869X_BIT_DETCTRL_PROTECT_MASK (~(1<<5)) #define AW869X_BIT_DETCTRL_PROTECT_NO_ACTION (1<<5) #define AW869X_BIT_DETCTRL_PROTECT_SHUTDOWN (0<<5) #define AW869X_BIT_DETCTRL_ADO_SLOT_MODE_MASK (~(1<<4)) #define AW869X_BIT_DETCTRL_ADO_SLOT_MODE_ENABLE (1<<4) #define AW869X_BIT_DETCTRL_ADO_SLOT_MODE_DISABLE (0<<4) #define AW869X_BIT_DETCTRL_VBAT_GO_MASK (~(1<<1)) #define AW869X_BIT_DETCTRL_VABT_GO_ENABLE (1<<1) #define AW869X_BIT_DETCTRL_VBAT_GO_DISBALE (0<<1) #define AW869X_BIT_DETCTRL_DIAG_GO_MASK (~(1<<0)) #define AW869X_BIT_DETCTRL_DIAG_GO_ENABLE (1<<0) #define AW869X_BIT_DETCTRL_DIAG_GO_DISABLE (0<<0) /* ADCTEST: reg0x66 */ #define AW869X_BIT_ADCTEST_VBAT_MODE_MASK (~(1<<6)) #define AW869X_BIT_ADCTEST_VBAT_HW_COMP (1<<6) #define AW869X_BIT_ADCTEST_VBAT_SW_COMP (0<<6) /* BEMF_NUM: reg0x78 */ #define AW869X_BIT_BEMF_NUM_BRK_MASK (~(15<<0)) /********************************************************* * * AW8692X Register Detail * *********************************************************/ /* RSTCFG: reg 0x01 RO */ #define AW86925_BIT_RSTCFG_PRE_VAL (0x00) #define AW86926_BIT_RSTCFG_PRE_VAL (0x01) #define AW86927_BIT_RSTCFG_PRE_VAL (0x02) #define AW86928_BIT_RSTCFG_PRE_VAL (0x03) #define AW86925_BIT_RSTCFG_VAL (0x80) #define AW86926_BIT_RSTCFG_VAL (0x81) #define AW86927_BIT_RSTCFG_VAL (0x82) #define AW86928_BIT_RSTCFG_VAL (0x83) /* SYSST: reg 0x01 RO */ #define AW8692X_BIT_SYSST_BST_SCPS (1<<7) #define AW8692X_BIT_SYSST_BST_OVPS (1<<6) #define AW8692X_BIT_SYSST_UVLS (1<<5) #define AW8692X_BIT_SYSST_FF_AES (1<<4) #define AW8692X_BIT_SYSST_FF_AFS (1<<3) #define AW8692X_BIT_SYSST_OCDS (1<<2) #define AW8692X_BIT_SYSST_OTS (1<<1) #define AW8692X_BIT_SYSST_DONES (1<<0) /* SYSINT: reg 0x02 RC */ #define AW8692X_BIT_SYSINT_BST_SCPI (1<<7) #define AW8692X_BIT_SYSINT_BST_OVPI (1<<6) #define AW8692X_BIT_SYSINT_UVLI (1<<5) #define AW8692X_BIT_SYSINT_FF_AEI (1<<4) #define AW8692X_BIT_SYSINT_FF_AFI (1<<3) #define AW8692X_BIT_SYSINT_OCDI (1<<2) #define AW8692X_BIT_SYSINT_OTI (1<<1) #define AW8692X_BIT_SYSINT_DONEI (1<<0) /* SYSINTM: reg 0x03 RW */ #define AW8692X_BIT_SYSINTM_BST_SCPM_MASK (~(1<<7)) #define AW8692X_BIT_SYSINTM_BST_SCPM_OFF (1<<7) #define AW8692X_BIT_SYSINTM_BST_SCPM_ON (0<<7) #define AW8692X_BIT_SYSINTM_BST_OVPM_MASK (~(1<<6)) #define AW8692X_BIT_SYSINTM_BST_OVPM_OFF (1<<6) #define AW8692X_BIT_SYSINTM_BST_OVPM_ON (0<<6) #define AW8692X_BIT_SYSINTM_UVLM_MASK (~(1<<5)) #define AW8692X_BIT_SYSINTM_UVLM_OFF (1<<5) #define AW8692X_BIT_SYSINTM_UVLM_ON (0<<5) #define AW8692X_BIT_SYSINTM_FF_AEM_MASK (~(1<<4)) #define AW8692X_BIT_SYSINTM_FF_AEM_OFF (1<<4) #define AW8692X_BIT_SYSINTM_FF_AEM_ON (0<<4) #define AW8692X_BIT_SYSINTM_FF_AFM_MASK (~(1<<3)) #define AW8692X_BIT_SYSINTM_FF_AFM_OFF (1<<3) #define AW8692X_BIT_SYSINTM_FF_AFM_ON (0<<3) #define AW8692X_BIT_SYSINTM_OCDM_MASK (~(1<<2)) #define AW8692X_BIT_SYSINTM_OCDM_OFF (1<<2) #define AW8692X_BIT_SYSINTM_OCDM_ON (0<<2) #define AW8692X_BIT_SYSINTM_OTM_MASK (~(1<<1)) #define AW8692X_BIT_SYSINTM_OTM_OFF (1<<1) #define AW8692X_BIT_SYSINTM_OTM_ON (0<<1) #define AW8692X_BIT_SYSINTM_DONEM_MASK (~(1<<0)) #define AW8692X_BIT_SYSINTM_DONEM_OFF (1<<0) #define AW8692X_BIT_SYSINTM_DONEM_ON (0<<0) /* SYSST2: reg 0x04 RO */ #define AW8692X_BIT_SYSST2_BST_OK (1<<4) #define AW8692X_BIT_SYSST2_VBG_OK (1<<3) #define AW8692X_BIT_SYSST2_LDO_OK (1<<2) #define AW8692X_BIT_SYSST2_FF_FULL (1<<1) #define AW8692X_BIT_SYSST2_FF_EMPTY (1<<0) /* PLAYCFG1: reg 0x06 RW */ #define AW8692X_BIT_PLAYCFG1_BST_MODE_MASK (~(1<<7)) #define AW8692X_BIT_PLAYCFG1_BST_MODE (1<<7) #define AW8692X_BIT_PLAYCFG1_BST_MODE_BYPASS (0<<7) #define AW8692X_BIT_PLAYCFG1_BST_VOUT_VREFSET_MASK (~(0x7F<<0)) #define AW8692X_BIT_PLAYCFG1_BST_VOUT_VREFSET (0x7F<<0) #define AW8692X_BIT_PLAYCFG1_BST_VOUT_6V (0x28) /* PLAYCFG3: reg 0x08 RW */ #define AW8692X_BIT_PLAYCFG3_ONEWIRE_COMP_MASK (~(1<<5)) #define AW8692X_BIT_PLAYCFG3_1908_ONEWIRE_MODE (1<<5) #define AW8692X_BIT_PLAYCFG3_2102_ONEWIRE_MODE (0<<5) #define AW8692X_BIT_PLAYCFG3_AUTO_BST_MASK (~(1<<4)) #define AW8692X_BIT_PLAYCFG3_AUTO_BST_ENABLE (1<<4) #define AW8692X_BIT_PLAYCFG3_AUTO_BST_DISABLE (0<<4) #define AW8692X_BIT_PLAYCFG3_STOP_MODE_MASK (~(1<<3)) #define AW8692X_BIT_PLAYCFG3_STOP_MODE_NOW (1<<3) #define AW8692X_BIT_PLAYCFG3_STOP_MODE_LATER (0<<3) #define AW8692X_BIT_PLAYCFG3_BRK_EN_MASK (~(1<<2)) #define AW8692X_BIT_PLAYCFG3_BRK_ENABLE (1<<2) #define AW8692X_BIT_PLAYCFG3_BRK_DISABLE (0<<2) #define AW8692X_BIT_PLAYCFG3_PLAY_MODE_MASK (~(3<<0)) #define AW8692X_BIT_PLAYCFG3_PLAY_MODE_STOP (3<<0) #define AW8692X_BIT_PLAYCFG3_PLAY_MODE_CONT (2<<0) #define AW8692X_BIT_PLAYCFG3_PLAY_MODE_RTP (1<<0) #define AW8692X_BIT_PLAYCFG3_PLAY_MODE_RAM (0<<0) /* PLAYCFG4: reg 0x09 RW */ #define AW8692X_BIT_PLAYCFG4_STOP_MASK (~(1<<1)) #define AW8692X_BIT_PLAYCFG4_STOP_ON (1<<1) #define AW8692X_BIT_PLAYCFG4_STOP_OFF (0<<1) #define AW8692X_BIT_PLAYCFG4_GO_MASK (~(1<<0)) #define AW8692X_BIT_PLAYCFG4_GO_ON (1<<0) #define AW8692X_BIT_PLAYCFG4_GO_OFF (0<<0) /* WAVCFG9-12: reg 0x12 - reg 0x15 RW */ #define AW8692X_BIT_WAVLOOP_SEQ_ODD_MASK (~(0x0F<<4)) #define AW8692X_BIT_WAVLOOP_SEQ_ODD_INIFINITELY (0x0F<<4) #define AW8692X_BIT_WAVLOOP_SEQ_EVEN_MASK (~(0x0F<<0)) #define AW8692X_BIT_WAVLOOP_SEQ_EVEN_INIFINITELY (0x0F<<0) #define AW8692X_WAVLOOP_INIFINITELY (0x0F<<0) /* WAVCFG9: reg 0x12 RW */ #define AW8692X_BIT_WAVCFG9_SEQ1LOOP_MASK (~(0x0F<<4)) #define AW8692X_BIT_WAVCFG9_SEQ1LOOP_INIFINITELY (0x0F<<4) #define AW8692X_BIT_WAVCFG9_SEQ2LOOP_MASK (~(0x0F<<0)) #define AW8692X_BIT_WAVCFG9_SEQ2LOOP_INIFINITELY (0x0F<<0) /***************** CONT *****************/ /* CONTCFG1: reg 0x18 RW */ #define AW8692X_BIT_CONTCFG1_BRK_BST_MD_MASK (~(1<<6)) #define AW8692X_BIT_CONTCFG1_BRK_BST_MD_ENABLE (1<<6) #define AW8692X_BIT_CONTCFG1_BRK_BST_MD_DISABLE (0<<6) #define AW8692X_BIT_CONTCFG1_EN_F0_DET_MASK (~(1<<5)) #define AW8692X_BIT_CONTCFG1_F0_DET_ENABLE (1<<5) #define AW8692X_BIT_CONTCFG1_F0_DET_DISABLE (0<<5) #define AW8692X_BIT_CONTCFG1_SIN_MODE_MASK (~(1<<1)) #define AW8692X_BIT_CONTCFG1_SIN_MODE_COS (1<<1) #define AW8692X_BIT_CONTCFG1_SIN_MODE_SINE (0<<1) #define AW8692X_BIT_CONTCFG1_EDGE_FRE_MASK (~(0x0F<<0)) /* CONTCFG5: reg 0x1C RW */ #define AW8692X_BIT_CONTCFG5_BST_BRK_GAIN_MASK (~(0x0F<<4)) #define AW8692X_BIT_CONTCFG5_BRK_GAIN_MASK (~(0x0F<<0)) /* CONTCFG6: reg 0x1D RW */ #define AW8692X_BIT_CONTCFG6_TRACK_EN_MASK (~(1<<7)) #define AW8692X_BIT_CONTCFG6_TRACK_ENABLE (1<<7) #define AW8692X_BIT_CONTCFG6_TRACK_DISABLE (0<<7) #define AW8692X_BIT_CONTCFG6_DRV1_LVL_MASK (~(0x7F<<0)) /* CONTCFG7: reg 0x1E RW */ #define AW8692X_BIT_CONTCFG7_DRV2_LVL_MASK (~(0x7F<<0)) /* CONTCFG13: reg 0x24 RW */ #define AW8692X_BIT_CONTCFG13_TSET_MASK (~(0x0F<<4)) #define AW8692X_BIT_CONTCFG13_BEME_SET_MASK (~(0x0F<<0)) /***************** RTP *****************/ /* RTPCFG1: reg 0x2D RW */ #define AW8692X_BIT_RTPCFG1_TWORTP_EN_MASK (~(1<<6)) #define AW8692X_BIT_RTPCFG1_TWORTP_ENABLE (1<<6) #define AW8692X_BIT_RTPCFG1_TWORTP_DISABLE (0<<6) #define AW8692X_BIT_RTPCFG1_BASE_ADDR_H_MASK (~(0x1F<<0)) /* RTPCFG3: reg 0x2F RW */ #define AW8692X_BIT_RTPCFG3_FIFO_AEH_MASK (~(0x0F<<4)) #define AW8692X_BIT_RTPCFG3_FIFO_AFH_MASK (~(0x0F<<0)) #define AW8692X_BIT_RTPCFG3_FIFO_AEH (0x0F<<4) #define AW8692X_BIT_RTPCFG3_FIFO_AFH (0x0F<<0) /***************** TRIGGER *****************/ #define AW8692X_BIT_TRG_ENABLE_MASK (~(1<<7)) #define AW8692X_BIT_TRG_ENABLE (1<<7) #define AW8692X_BIT_TRG_DISABLE (0<<7) #define AW8692X_BIT_TRG_SEQ_MASK (~(0x7F<<0)) /* TRGCFG1: reg 0x33 RW */ #define AW8692X_BIT_TRGCFG1_TRG1_POS_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG1_TRG1_POS_ENABLE (1<<7) #define AW8692X_BIT_TRGCFG1_TRG1_POS_DISABLE (0<<7) #define AW8692X_BIT_TRGCFG1_TRG1SEQ_P_MASK (~(0x7F<<0)) /* TRGCFG2: reg 0x34 RW */ #define AW8692X_BIT_TRGCFG2_TRG2_POS_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG2_TRG2_POS_ENABLE (1<<7) #define AW8692X_BIT_TRGCFG2_TRG2_POS_DISABLE (0<<7) #define AW8692X_BIT_TRGCFG2_TRG2SEQ_P_MASK (~(0x7F<<0)) /* TRGCFG3: reg 0x35 RW */ #define AW8692X_BIT_TRGCFG3_TRG3_POS_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG3_TRG3_POS_ENABLE (1<<7) #define AW8692X_BIT_TRGCFG3_TRG3_POS_DISABLE (0<<7) #define AW8692X_BIT_TRGCFG3_TRG3SEQ_P_MASK (~(0x7F<<0)) /* TRGCFG4: reg 0x36 RW */ #define AW8692X_BIT_TRGCFG4_TRG1_NEG_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG4_TRG1_NEG_ENABLE (1<<7) #define AW8692X_BIT_TRGCFG4_TRG1_NEG_DISABLE (0<<7) #define AW8692X_BIT_TRGCFG4_TRG1SEQ_N_MASK (~(0x7F<<0)) /* TRGCFG5: reg 0x37 RW */ #define AW8692X_BIT_TRGCFG5_TRG2_NEG_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG5_TRG2_NEG_ENABLE (1<<7) #define AW8692X_BIT_TRGCFG5_TRG2_NEG_DISABLE (0<<7) #define AW8692X_BIT_TRGCFG5_TRG2SEQ_N_MASK (~(0x7F<<0)) /* TRGCFG6: reg 0x38 RW */ #define AW8692X_BIT_TRGCFG6_TRG3_NEG_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG6_TRG3_NEG_ENABLE (1<<7) #define AW8692X_BIT_TRGCFG6_TRG3_NEG_DISABLE (0<<7) #define AW8692X_BIT_TRGCFG6_TRG3SEQ_N_MASK (~(0x7F<<0)) /* TRGCFG7: reg 0x39 RW */ #define AW8692X_BIT_TRGCFG7_TRG1_POLAR_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG7_TRG1_POLAR_NEG (1<<7) #define AW8692X_BIT_TRGCFG7_TRG1_POLAR_POS (0<<7) #define AW8692X_BIT_TRGCFG7_TRG1_MODE_MASK (~(1<<6)) #define AW8692X_BIT_TRGCFG7_TRG1_MODE_LEVEL (1<<6) #define AW8692X_BIT_TRGCFG7_TRG1_MODE_EDGE (0<<6) #define AW8692X_BIT_TRGCFG7_TRG1_AUTO_BRK_MASK (~(1<<5)) #define AW8692X_BIT_TRGCFG7_TRG1_AUTO_BRK_ENABLE (1<<5) #define AW8692X_BIT_TRGCFG7_TRG1_AUTO_BRK_DISABLE (0<<5) #define AW8692X_BIT_TRGCFG7_TRG1_BST_MASK (~(1<<4)) #define AW8692X_BIT_TRGCFG7_TRG1_BST_ENABLE (1<<4) #define AW8692X_BIT_TRGCFG7_TRG1_BST_DISABLE (0<<4) #define AW8692X_BIT_TRGCFG7_TRG2_POLAR_MASK (~(1<<3)) #define AW8692X_BIT_TRGCFG7_TRG2_POLAR_NEG (1<<3) #define AW8692X_BIT_TRGCFG7_TRG2_POLAR_POS (0<<3) #define AW8692X_BIT_TRGCFG7_TRG2_MODE_MASK (~(1<<2)) #define AW8692X_BIT_TRGCFG7_TRG2_MODE_LEVEL (1<<2) #define AW8692X_BIT_TRGCFG7_TRG2_MODE_EDGE (0<<2) #define AW8692X_BIT_TRGCFG7_TRG2_AUTO_BRK_MASK (~(1<<1)) #define AW8692X_BIT_TRGCFG7_TRG2_AUTO_BRK_ENABLE (1<<1) #define AW8692X_BIT_TRGCFG7_TRG2_AUTO_BRK_DISABLE (0<<1) #define AW8692X_BIT_TRGCFG7_TRG2_BST_MASK (~(1<<0)) #define AW8692X_BIT_TRGCFG7_TRG2_BST_ENABLE (1<<0) #define AW8692X_BIT_TRGCFG7_TRG2_BST_DISABLE (0<<0) /* TRGCFG8: reg 0x3A RW */ #define AW8692X_BIT_TRGCFG8_TRG3_POLAR_MASK (~(1<<7)) #define AW8692X_BIT_TRGCFG8_TRG3_POLAR_NEG (1<<7) #define AW8692X_BIT_TRGCFG8_TRG3_POLAR_POS (0<<7) #define AW8692X_BIT_TRGCFG8_TRG3_MODE_MASK (~(1<<6)) #define AW8692X_BIT_TRGCFG8_TRG3_MODE_LEVEL (1<<6) #define AW8692X_BIT_TRGCFG8_TRG3_MODE_EDGE (0<<6) #define AW8692X_BIT_TRGCFG8_TRG3_AUTO_BRK_MASK (~(1<<5)) #define AW8692X_BIT_TRGCFG8_TRG3_AUTO_BRK_ENABLE (1<<5) #define AW8692X_BIT_TRGCFG8_TRG3_AUTO_BRK_DISABLE (0<<5) #define AW8692X_BIT_TRGCFG8_TRG3_BST_MASK (~(1<<4)) #define AW8692X_BIT_TRGCFG8_TRG3_BST_ENABLE (1<<4) #define AW8692X_BIT_TRGCFG8_TRG3_BST_DISABLE (0<<4) #define AW8692X_BIT_TRGCFG8_TRG_ONEWIRE_MASK (~(1<<3)) #define AW8692X_BIT_TRGCFG8_TRG_ONEWIRE_ENABLE (1<<3) #define AW8692X_BIT_TRGCFG8_TRG_ONEWIRE_DISABLE (0<<3) #define AW8692X_BIT_TRGCFG8_TRG1_STOP_MASK (~(1<<2)) #define AW8692X_BIT_TRGCFG8_TRG1_STOP (1<<2) #define AW8692X_BIT_TRGCFG8_TRG2_STOP_MASK (~(1<<1)) #define AW8692X_BIT_TRGCFG8_TRG2_STOP (1<<1) #define AW8692X_BIT_TRGCFG8_TRG3_STOP_MASK (~(1<<0)) #define AW8692X_BIT_TRGCFG8_TRG3_STOP (1<<0) /* GLBCFG2: reg 0x3C RW */ /* START_DLY */ #define AW8692X_BIT_START_DLY_20US (0x01) #define AW8692X_BIT_START_DLY_2P5MS (0x75) /* GLBCFG4: reg 0x3E RW */ #define AW8692X_BIT_GLBCFG4_GO_PRIO_MASK (~(3<<6)) #define AW8692X_BIT_GLBCFG4_TRG3_PRIO_MASK (~(3<<4)) #define AW8692X_BIT_GLBCFG4_TRG2_PRIO_MASK (~(3<<2)) #define AW8692X_BIT_GLBCFG4_TRG1_PRIO_MASK (~(3<<0)) /* GLBRD5: reg 0x3F R0 */ /* GLB_STATE [3:0] */ #define AW8692X_BIT_GLBRD5_STATE_MASK (~(15<<0)) #define AW8692X_BIT_GLBRD5_STATE_STANDBY (0<<0) #define AW8692X_BIT_GLBRD5_STATE_WAKEUP (1<<0) #define AW8692X_BIT_GLBRD5_STATE_STARTUP (2<<0) #define AW8692X_BIT_GLBRD5_STATE_WAIT (3<<0) #define AW8692X_BIT_GLBRD5_STATE_CONT_GO (6<<0) #define AW8692X_BIT_GLBRD5_STATE_RAM_GO (7<<0) #define AW8692X_BIT_GLBRD5_STATE_RTP_GO (8<<0) #define AW8692X_BIT_GLBRD5_STATE_TRIG_GO (9<<0) #define AW8692X_BIT_GLBRD5_STATE_I2S_GO (10<<0) #define AW8692X_BIT_GLBRD5_STATE_BRAKE (11<<0) #define AW8692X_BIT_GLBRD5_STATE_END (12<<0) /* RAMADDRH: reg 0x40 RWS */ #define AW8692X_BIT_RAMADDRH_MASK (~(0x1F<<0)) /* SYSCTRL2: reg 0x44 RWS */ #define AW8692X_BIT_SYSCTRL2_SLOT_CHSEL_MASK (~(1<<5)) #define AW8692X_BIT_SYSCTRL2_RTP_SLOT_ONE (0<<5) #define AW8692X_BIT_SYSCTRL2_RTP_SLOT_TWO (1<<5) #define AW8692X_BIT_SYSCTRL2_RCK_FRE (3<<2) /* SYSCTRL3: reg 0x45 RW */ #define AW8692X_BIT_SYSCTRL3_WCK_PIN_MASK (~(1<<7)) #define AW8692X_BIT_SYSCTRL3_WCK_PIN_ON (1<<7) #define AW8692X_BIT_SYSCTRL3_WCK_PIN_OFF (0<<7) #define AW8692X_BIT_SYSCTRL3_WAKE_MASK (~(1<<6)) #define AW8692X_BIT_SYSCTRL3_WAKE_ON (1<<6) #define AW8692X_BIT_SYSCTRL3_WAKE_OFF (0<<6) #define AW8692X_BIT_SYSCTRL3_STANDBY_MASK (~(1<<5)) #define AW8692X_BIT_SYSCTRL3_STANDBY_ON (1<<5) #define AW8692X_BIT_SYSCTRL3_STANDBY_OFF (0<<5) #define AW8692X_BIT_SYSCTRL3_RTP_DLY_MASK (~(3<<3)) #define AW8692X_BIT_SYSCTRL3_EN_RAMINIT_MASK (~(1<<2)) #define AW8692X_BIT_SYSCTRL3_EN_RAMINIT_ON (1<<2) #define AW8692X_BIT_SYSCTRL3_EN_RAMINIT_OFF (0<<2) #define AW8692X_BIT_SYSCTRL3_EN_FIR_MASK (~(1<<1)) #define AW8692X_BIT_SYSCTRL3_EN_FIR_ON (1<<1) #define AW8692X_BIT_SYSCTRL3_EN_FIR_OFF (0<<1) #define AW8692X_BIT_SYSCTRL3_WAKE_MODE_MASK (~(1<<0)) #define AW8692X_BIT_SYSCTRL3_WAKE_MODE_ON (1<<0) #define AW8692X_BIT_SYSCTRL3_WAKE_MODE_OFF (0<<0) /* SYSCTRL4: reg 0x46 RW */ #define AW8692X_BIT_SYSCTRL4_EN_INTN_CLKOUT_MASK (~(1<<7)) #define AW8692X_BIT_SYSCTRL4_EN_INTN_CLKOUT_ON (1<<7) #define AW8692X_BIT_SYSCTRL4_EN_INTN_CLKOUT_OFF (0<<7) #define AW8692X_BIT_SYSCTRL4_WAVDAT_MODE_MASK (~(3<<5)) #define AW8692X_BIT_SYSCTRL4_WAVDAT_12K (2<<5) #define AW8692X_BIT_SYSCTRL4_WAVDAT_48K (1<<5) #define AW8692X_BIT_SYSCTRL4_WAVDAT_24K (0<<5) #define AW8692X_BIT_SYSCTRL4_INT_EDGE_MODE_MASK (~(1<<4)) #define AW8692X_BIT_SYSCTRL4_INT_EDGE_MODE_POS (0<<4) #define AW8692X_BIT_SYSCTRL4_INT_EDGE_MODE_BOTH (1<<4) #define AW8692X_BIT_SYSCTRL4_INT_MODE_MASK (~(1<<3)) #define AW8692X_BIT_SYSCTRL4_INT_MODE_EDGE (1<<3) #define AW8692X_BIT_SYSCTRL4_INT_MODE_LEVEL (0<<3) /* SYSCTRL5: reg 0x47 RW */ #define AW8692X_REG_SYSCTRL5_INIT_VAL (0x5A) #define AW8692X_BIT_SYSCTRL5_EN_BRO_ADDR_MASK (~(1<<7)) #define AW8692X_BIT_SYSCTRL5_EN_BRO_ADDR_ON (1<<7) #define AW8692X_BIT_SYSCTRL5_EN_BRO_ADDR_OFF (0<<7) #define AW8692X_BIT_SYSCTRL5_BROADCAST_ADDR_MASK (~(0x7F<<0)) /* PWMCFG1: reg 0x48 RW */ #define AW8692X_BIT_PWMCFG1_PRC_EN_MASK (~(1<<7)) #define AW8692X_BIT_PWMCFG1_PRC_ENABLE (1<<7) #define AW8692X_BIT_PWMCFG1_PRC_DISABLE (0<<7) #define AW8692X_BIT_PWMCFG1_PRCTIME_MASK (~(0x7F<<0)) #define AW8692X_BIT_PWMCFG1_INIT_VAL (0xA0) /* PWMCFG2: reg 0x49 RW */ #define AW8692X_BIT_PWMCFG2_PRCT_MODE_MASK (~(1<<6)) #define AW8692X_BIT_PWMCFG2_PRCT_MODE_VALID (0<<6) #define AW8692X_BIT_PWMCFG2_PRCT_MODE_INVALID (1<<6) #define AW8692X_BIT_PWMCFG2_REF_SEL_MASK (~(1<<5)) #define AW8692X_BIT_PWMCFG2_REF_SEL_TRIANGLE (1<<5) #define AW8692X_BIT_PWMCFG2_REF_SEL_SAWTOOTH (0<<5) #define AW8692X_BIT_PWMCFG2_PD_HWM_MASK (~(1<<4)) #define AW8692X_BIT_PWMCFG2_PD_HWM_ON (1<<4) #define AW8692X_BIT_PWMCFG2_PWMOE_MASK (~(1<<3)) #define AW8692X_BIT_PWMCFG2_PWMOE_ON (1<<3) #define AW8692X_BIT_PWMCFG2_PWMFRC_MASK (~(7<<0)) /* PWMCFG3: reg 0x4A RW */ #define AW8692X_BIT_PWMCFG3_PR_EN_MASK (~(1<<7)) #define AW8692X_BIT_PWMCFG3_PR_ENABLE (1<<7) #define AW8692X_BIT_PWMCFG3_PR_DISABLE (0<<7) #define AW8692X_BIT_PWMCFG3_PRLVL_MASK (~(0x7F<<0)) /* VBATCTRL: reg 0x4C RW */ #define AW8692X_BIT_VBATCTRL_VBAT_PRO_MASK (~(1<<7)) #define AW8692X_BIT_VBATCTRL_VBAT_PRO_ENABLE (1<<7) #define AW8692X_BIT_VBATCTRL_VBAT_PRO_DISABLE (0<<7) #define AW8692X_BIT_VBATCTRL_VBAT_MODE_MASK (~(1<<6)) #define AW8692X_BIT_VBATCTRL_VBAT_MODE_HW (1<<6) #define AW8692X_BIT_VBATCTRL_VBAT_MODE_SW (0<<6) #define AW8692X_BIT_VBATCTRL_VBAT_MODE_CON_MASK (~(1<<5)) #define AW8692X_BIT_VBATCTRL_VBAT_MODE_CON_DURING (1<<5) #define AW8692X_BIT_VBATCTRL_VBAT_MODE_CON_BEFORE (0<<5) #define AW8692X_BIT_VBATCTRL_DELTA_VBAT_MASK (~(1<<4)) #define AW8692X_BIT_VBATCTRL_DELTA_VBAT_0P2V (1<<4) #define AW8692X_BIT_VBATCTRL_DELTA_VBAT_0P1V (0<<4) #define AW8692X_BIT_VBATCTRL_REL_VBAT_MASK (~(3<<2)) #define AW8692X_BIT_VBATCTRL_ABS_VBAT_MASK (~(3<<0)) /* DETCFG1: reg 0x4D RW */ #define AW8692X_BIT_DETCFG1_VBAT_REF_MASK (~(7<<4)) #define AW8692X_BIT_DETCFG1_ADC_FS_MASK (~(3<<2)) #define AW8692X_BIT_DETCFG1_ADC_FS (3<<2) #define AW8692X_BIT_DETCFG1_ADC_FS_192KHZ (0<<2) #define AW8692X_BIT_DETCFG1_ADC_FS_96KHZ (1<<2) #define AW8692X_BIT_DETCFG1_ADC_FS_48KHZ (2<<2) #define AW8692X_BIT_DETCFG1_ADC_FS_24KHZ (3<<2) #define AW8692X_BIT_DETCFG1_DET_GO_MASK (~(3<<0)) #define AW8692X_BIT_DETCFG1_DET_GO_NA (0<<0) #define AW8692X_BIT_DETCFG1_DET_GO_MASK (~(3<<0)) #define AW8692X_BIT_DETCFG1_DET_GO_NA (0<<0) #define AW8692X_BIT_DETCFG1_DET_GO_DET_SEQ0 (1<<0) /* DETCFG2: reg 0x4E RW */ #define AW8692X_BIT_DETCFG2_DET_SEQ0_MASK (~(0xF<<3)) #define AW8692X_BIT_DETCFG2_DET_SEQ0_VBAT (0<<3) #define AW8692X_BIT_DETCFG2_DET_SEQ0_PVDD (1<<3) #define AW8692X_BIT_DETCFG2_DET_SEQ0_TRIG1 (2<<3) #define AW8692X_BIT_DETCFG2_DET_SEQ0_RL (3<<3) #define AW8692X_BIT_DETCFG2_DET_SEQ0_OS (4<<3) #define AW8692X_BIT_DETCFG2_DET_SEQ0_VOUT (5<<3) #define AW8692X_BIT_DETCFG2_DET_SEQ0_FTS (6<<3) #define AW8692X_BIT_DETCFG2_D2S_GAIN_MASK (~(7<<0)) #define AW8692X_BIT_DETCFG2_D2S_GAIN (7<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_1 (0<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_2 (1<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_4 (2<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_8 (3<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_10 (4<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_16 (5<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_20 (6<<0) #define AW8692X_BIT_DETCFG2_D2S_GAIN_40 (7<<0) /* DETRD1: reg 0x4F RW */ #define AW8692X_BIT_DETRD1_AVG_DATA (3<<0) /* TRIMCFG1: reg 0x52 RW */ #define AW8692X_BIT_TRIMCFG1_RL_TRIM_SRC_MASK (~(0X01<<7)) #define AW8692X_BIT_TRIMCFG1_RL_TRIM_SRC_EFUSE (0<<7) #define AW8692X_BIT_TRIMCFG1_RL_TRIM_SRC_REG (1<<7) /* TMCFG: reg 0x5B RW */ #define AW8692X_BIT_TMCFG_TM_UNLOCK (0x7d) #define AW8692X_BIT_TMCFG_TM_LOCK (0x00) /* reg 0x71 */ #define AW8692X_BIT_ANACFG12_INIT_VAL (0x93) /* ANACFG13: reg 0x72 RW*/ #define AW8692X_BIT_BSTCFG1_BST_PC_MASK (~(0xF0<<0)) #define AW8692X_BIT_BSTCFG1_BST_PEAKCUR_3P5A (6<<4) /* reg 0x74 */ #define AW8692X_BIT_ANACFG15_INIT_VAL (0x89) /* reg 0x75 */ #define AW8692X_BIT_ANACFG16_INIT_VAL (0x88) /* ANACFG20: reg 0x79 RW */ #define AW8692X_BIT_ANACFG20_TRIM_LRA_MASK (~(0x3F<<0)) #define AW8692X_BIT_ANACFG20_TRIM_LRA (0x3F<<0) #endif